Spark Logic

MOS 6502 connection guide

MOS 6502 DIP-40 wiring guide with power, signal assignments, and bench checks.

DIP-40

40 contacts Current package

MOS Technology / Commodore Semiconductor Group · MPS plastic and MCS ceramic use the same top-view 40-pin map.

1 MHz maximum. MPS6502 plastic or MCS6502 ceramic.

5 V supply and bypass

Required

Supply VCC from a regulated 5 V rail and connect both VSS contacts. Fit a 100 nF ceramic bypass close to VCC and a short ground return.

100 nF between +5 V and 0 V+5 V100 nF0 V

Bench checks

  • With power off, check continuity from pins 1 and 21 to the ground rail.
  • Measure 4.75–5.25 V at pin 8 before releasing reset. The bypass capacitor is a board-level design choice.

Commodore Component Data Catalog (1981), pp. 2-7 and 2-11

Connection scenarios

Open-drain IRQ and NMI

Use independent open-drain outputs and a separate 3 kΩ pull-up for each interrupt input. A 3 kΩ, 1% resistor rated at 0.125 W has ample margin over the roughly 9.2 mW worst-case static dissipation at 5.25 V.

R1 3 kΩ between +5 V and IRQ+5 VR1 3 kΩIRQ
R2 3 kΩ between +5 V and NMI+5 VR2 3 kΩNMI

Bench checks

  • Verify each line idles high and the sink can pull it below 0.4 V at approximately 1.75 mA.
  • Initialize the stack and install vectors before asserting interrupt sources. IRQ requires the I flag to be cleared by software.

Commodore Component Data Catalog (1981), pp. 2-2 and 2-7

DIP-40 wiring map

Highlighted contacts are used in the required step or selected circuit. Select a contact to inspect it.

Top view · Pin 1 at upper left · Schematic outline
Selected pin details

6 · /NMI

Input · Inputs

Falling-edge nonmaskable interrupt request. Use the specified 3 kΩ pull-up for an open-drain source.

Commodore Component Data Catalog (1981), pp. 2-1–2-2 and 2-11

Electrical limits · Pin in the reference

Models and documents

Covers the MOS Technology / CSG NMOS 6502 map. The related 6503–6507 and 6512–6515 have their own maps in the catalog. WDC W65C02S is a distinct CMOS part with different pin assignments and timing.

6502
1 MHz maximum. MPS6502 plastic or MCS6502 ceramic.
6502A
2 MHz maximum. MPS6502A plastic or MCS6502A ceramic.
6502B
3 MHz maximum. MPS6502B plastic or MCS6502B ceramic. See the 1982–1983 catalog for 3 MHz timing.
  • Commodore Component Data Catalog (1981)· Manufacturer catalog scan. Cross-reference p. 1-3, MPU signals and electrical data pp. 2-1–2-10, 6502 pinout p. 2-11. Scan SHA-256 ddc2be52d8b14c99b28e0a2d2d116bcaa1c4c241b4005e06b4459d96e2566902.
  • MOS Technology Data Catalog (1982–1983)· Manufacturer data catalog. NMOS MPU order codes on p. 2-14 and 1, 2 and 3 MHz timing on p. 2-18. Scan SHA-256 1a6152082a15479e893a9c3391cafc4aba135dfae0613a96fbcbe12ac44248ca.
  • WDC W65C02S datasheet· Separate CMOS derivative. Compare its pin assignments and electrical conditions before designing a replacement.