MOS 6502 pinout

Original NMOS 6502 microprocessor with an 8-bit data bus and 16-bit address bus. It addresses 64 KiB of external memory and I/O and requires external RAM and ROM.

DIP-40

40 contacts Current package

MOS Technology / Commodore Semiconductor Group · MPS plastic and MCS ceramic use the same top-view 40-pin map.

2 MHz maximum. MPS6502A plastic or MCS6502A ceramic.

DIP-40 pinout

Top view · Pin 1 at upper left · Schematic outline

Selected pin details

16 · A7

Output · Outputs

Address bit 7 (AB7 in the datasheet). The external decoder uses this line to select memory and I/O.

Commodore Component Data Catalog (1981), pp. 2-1–2-2 and 2-11

Electrical limits · Link to this pin

All 40 pins

Pin	Signal	Direction	Function
1	VSS Supply return	Supply return	Connect both VSS pins to the 0 V rail.
2	RDY Input	Input	Keep high for normal operation. A low sampled during a read holds the processor on that cycle. A pending write must complete before a read cycle can stop.
3	Φ1 OUT Output	Output	Phase-one output generated from Φ0 IN. Never drive this pin.
4	/IRQ Input	Input	Active-low level-sensitive interrupt request. IRQ is masked by the I flag after reset. Use the specified 3 kΩ pull-up for an open-drain source.
5	NC None	None	Leave this pin unconnected.
6	/NMI Input	Input	Falling-edge nonmaskable interrupt request. Use the specified 3 kΩ pull-up for an open-drain source.
7	SYNC Output	Output	High on an opcode fetch. An external circuit can use SYNC to time a pause through RDY for single-instruction stepping.
8	VCC Supply	Supply	Regulated 5 V supply. Decouple to VSS close to the package.
9	A0 Output	Output	Address bit 0 (AB0 in the datasheet). The external decoder uses this line to select memory and I/O.
10	A1 Output	Output	Address bit 1 (AB1 in the datasheet). The external decoder uses this line to select memory and I/O.
11	A2 Output	Output	Address bit 2 (AB2 in the datasheet). The external decoder uses this line to select memory and I/O.
12	A3 Output	Output	Address bit 3 (AB3 in the datasheet). The external decoder uses this line to select memory and I/O.
13	A4 Output	Output	Address bit 4 (AB4 in the datasheet). The external decoder uses this line to select memory and I/O.
14	A5 Output	Output	Address bit 5 (AB5 in the datasheet). The external decoder uses this line to select memory and I/O.
15	A6 Output	Output	Address bit 6 (AB6 in the datasheet). The external decoder uses this line to select memory and I/O.
16	A7 Output	Output	Address bit 7 (AB7 in the datasheet). The external decoder uses this line to select memory and I/O.
17	A8 Output	Output	Address bit 8 (AB8 in the datasheet). The external decoder uses this line to select memory and I/O.
18	A9 Output	Output	Address bit 9 (AB9 in the datasheet). The external decoder uses this line to select memory and I/O.
19	A10 Output	Output	Address bit 10 (AB10 in the datasheet). The external decoder uses this line to select memory and I/O.
20	A11 Output	Output	Address bit 11 (AB11 in the datasheet). The external decoder uses this line to select memory and I/O.
21	VSS Supply return	Supply return	Connect both VSS pins to the 0 V rail.
22	A12 Output	Output	Address bit 12 (AB12 in the datasheet). The external decoder uses this line to select memory and I/O.
23	A13 Output	Output	Address bit 13 (AB13 in the datasheet). The external decoder uses this line to select memory and I/O.
24	A14 Output	Output	Address bit 14 (AB14 in the datasheet). The external decoder uses this line to select memory and I/O.
25	A15 Output	Output	Address bit 15 (AB15 in the datasheet). The external decoder uses this line to select memory and I/O.
26	D7 Bidirectional	Bidirectional	Data bit 7 (DB7 in the datasheet). External memory or I/O drives it on reads, and the CPU drives it on writes.
27	D6 Bidirectional	Bidirectional	Data bit 6 (DB6 in the datasheet). External memory or I/O drives it on reads, and the CPU drives it on writes.
28	D5 Bidirectional	Bidirectional	Data bit 5 (DB5 in the datasheet). External memory or I/O drives it on reads, and the CPU drives it on writes.
29	D4 Bidirectional	Bidirectional	Data bit 4 (DB4 in the datasheet). External memory or I/O drives it on reads, and the CPU drives it on writes.
30	D3 Bidirectional	Bidirectional	Data bit 3 (DB3 in the datasheet). External memory or I/O drives it on reads, and the CPU drives it on writes.
31	D2 Bidirectional	Bidirectional	Data bit 2 (DB2 in the datasheet). External memory or I/O drives it on reads, and the CPU drives it on writes.
32	D1 Bidirectional	Bidirectional	Data bit 1 (DB1 in the datasheet). External memory or I/O drives it on reads, and the CPU drives it on writes.
33	D0 Bidirectional	Bidirectional	Data bit 0 (DB0 in the datasheet). External memory or I/O drives it on reads, and the CPU drives it on writes.
34	R/W Output	Output	High for read, low for write. The pin is specified as valid after the power-up reset hold time.
35	NC None	None	Leave this pin unconnected.
36	NC None	None	Leave this pin unconnected.
37	Φ0 IN Input	Input	Single-phase time base for the on-chip two-phase clock. Keep the clock running during reset and use the timing table for the marked speed grade.
38	SO Input	Input	A falling edge sets the processor status overflow flag. Hold at a defined high level when unused.
39	Φ2 OUT Output	Output	Phase-two output generated from Φ0 IN. Used as the timing reference for the external data bus.
40	/RES Input	Input	Hold low during power-up. After release and initialization, the CPU reads the low byte from 0xFFFC and the high byte from 0xFFFD.

Signal assignments

External memory bus

16 separate address lines, 8 bidirectional data lines, R/W and the Φ2 timing reference. Select only one data source on a read and release it on a write.

Clock

Feed the single-phase source to Φ0 IN. The chip generates both clock outputs.

Interrupts

IRQ is level-sensitive and maskable. NMI is edge-sensitive. Both are active low.

Reset and execution control

Use reset at power-up. SYNC identifies opcode fetches, and RDY pauses reads. SO can set the overflow flag independently of the instruction stream.

Electrical limits

Parameter	Limit	Conditions and source
Operating supply4.75–5.25 V	4.75–5.25 V	VCC relative to VSS. Published operating temperature range 0–70 °C. MOS Technology Data Catalog (1982–1983), p. 2-16
Input operating levelsLOW ≤ 0.4 V, HIGH ≥ 2.4 V	LOW ≤ 0.4 V, HIGH ≥ 2.4 V	Logic and Φ0 IN at 0–70 °C. The catalog separately lists 0.8 V and 2.0 V threshold limits for RES, IRQ, NMI, RDY, SO and data. MOS Technology Data Catalog (1982–1983), p. 2-16
Logic output levelsLOW ≤ 0.4 V at 1.6 mA, HIGH ≥ 2.4 V at 100 µA source	LOW ≤ 0.4 V at 1.6 mA, HIGH ≥ 2.4 V at 100 µA source	A0–A15, D0–D7, R/W and SYNC at VCC = 4.75 V. Check clock loading separately. MOS Technology Data Catalog (1982–1983), p. 2-16
Clock frequency50 kHz minimum, 1 / 2 / 3 MHz maximum	50 kHz minimum, 1 / 2 / 3 MHz maximum	Maximum by grade. Keep the clock running during reset and when using RDY. MOS Technology Data Catalog (1982–1983), pp. 2-14 and 2-18
Absolute voltage limits−0.3 to +7.0 V	−0.3 to +7.0 V	VCC and input stress limits relative to VSS. Use the operating values for circuit design. Commodore Component Data Catalog (1981), p. 2-6
Interrupt pull-ups3 kΩ each to VCC	3 kΩ each to VCC	IRQ and NMI. At 5.25 V the external open-drain device must sink about 1.75 mA at low output voltage. Commodore Component Data Catalog (1981), p. 2-7 and signal descriptions

Models and documents

Covers the MOS Technology / CSG NMOS 6502 map. The related 6503–6507 and 6512–6515 have their own maps in the catalog. WDC W65C02S is a distinct CMOS part with different pin assignments and timing.

6502: 1 MHz maximum. MPS6502 plastic or MCS6502 ceramic.
6502A: 2 MHz maximum. MPS6502A plastic or MCS6502A ceramic.
6502B: 3 MHz maximum. MPS6502B plastic or MCS6502B ceramic. See the 1982–1983 catalog for 3 MHz timing.

Commodore Component Data Catalog (1981)· Manufacturer catalog scan. Cross-reference p. 1-3, MPU signals and electrical data pp. 2-1–2-10, 6502 pinout p. 2-11. Scan SHA-256 ddc2be52d8b14c99b28e0a2d2d116bcaa1c4c241b4005e06b4459d96e2566902.
MOS Technology Data Catalog (1982–1983)· Manufacturer data catalog. NMOS MPU order codes on p. 2-14 and 1, 2 and 3 MHz timing on p. 2-18. Scan SHA-256 1a6152082a15479e893a9c3391cafc4aba135dfae0613a96fbcbe12ac44248ca.
WDC W65C02S datasheet· Separate CMOS derivative. Compare its pin assignments and electrical conditions before designing a replacement.