Motorola MC6800 pinout

8-bit MPU with 64 KiB of external address space, an 8-bit data bus and an externally driven two-phase clock. It requires external RAM and ROM.

DIP-40

40 contacts Current package

Motorola · P plastic (Case 711), S CERDIP (Case 734) and L ceramic (Case 715) share the top-view pin assignment.

2.0 MHz maximum. MC68B00P/S/L (0–70 °C) in DS9471-R2.

DIP-40 pinout

Top view · Pin 1 at upper left · Schematic outline

Selected pin details

23 · A13

Output · Outputs

Address bit 13. Qualify the address with VMA. HALT or TSC can release this output.

Motorola MC6800 data sheet DS9471-R2, pin assignment and signal descriptions

Electrical limits · Link to this pin

All 40 pins

Pin	Signal	Direction	Function
1	VSS Supply return	Supply return	Connect both VSS contacts to the 0 V rail.
2	/HALT Input	Input	Low stops instruction execution and eventually releases the bus, indicated by BA high. The clocks must continue while halted.
3	Φ1 Input	Input	Phase one of an external non-overlapping two-phase clock. This input needs a near-rail high and can present up to 35 pF.
4	/IRQ Input	Input	Active-low level-sensitive maskable interrupt. The IRQ mask is set during reset.
5	VMA Output	Output	High marks a valid external address. Low after the power-up reset settling interval and when TSC is asserted.
6	/NMI Input	Input	Falling-edge nonmaskable interrupt input. Use a defined high level when unused.
7	BA Output	Output	High indicates that the bus is available when the CPU is halted or waiting. TSC high forces BA low.
8	VCC Supply	Supply	Regulated 5 V supply. Decouple to VSS close to the package.
9	A0 Output	Output	Address bit 0. Qualify the address with VMA. HALT or TSC can release this output.
10	A1 Output	Output	Address bit 1. Qualify the address with VMA. HALT or TSC can release this output.
11	A2 Output	Output	Address bit 2. Qualify the address with VMA. HALT or TSC can release this output.
12	A3 Output	Output	Address bit 3. Qualify the address with VMA. HALT or TSC can release this output.
13	A4 Output	Output	Address bit 4. Qualify the address with VMA. HALT or TSC can release this output.
14	A5 Output	Output	Address bit 5. Qualify the address with VMA. HALT or TSC can release this output.
15	A6 Output	Output	Address bit 6. Qualify the address with VMA. HALT or TSC can release this output.
16	A7 Output	Output	Address bit 7. Qualify the address with VMA. HALT or TSC can release this output.
17	A8 Output	Output	Address bit 8. Qualify the address with VMA. HALT or TSC can release this output.
18	A9 Output	Output	Address bit 9. Qualify the address with VMA. HALT or TSC can release this output.
19	A10 Output	Output	Address bit 10. Qualify the address with VMA. HALT or TSC can release this output.
20	A11 Output	Output	Address bit 11. Qualify the address with VMA. HALT or TSC can release this output.
21	VSS Supply return	Supply return	Connect both VSS contacts to the 0 V rail.
22	A12 Output	Output	Address bit 12. Qualify the address with VMA. HALT or TSC can release this output.
23	A13 Output	Output	Address bit 13. Qualify the address with VMA. HALT or TSC can release this output.
24	A14 Output	Output	Address bit 14. Qualify the address with VMA. HALT or TSC can release this output.
25	A15 Output	Output	Address bit 15. Qualify the address with VMA. HALT or TSC can release this output.
26	D7 Bidirectional	Bidirectional	Data bit 7. External memory drives during reads, and the CPU can drive during writes while DBE is high.
27	D6 Bidirectional	Bidirectional	Data bit 6. External memory drives during reads, and the CPU can drive during writes while DBE is high.
28	D5 Bidirectional	Bidirectional	Data bit 5. External memory drives during reads, and the CPU can drive during writes while DBE is high.
29	D4 Bidirectional	Bidirectional	Data bit 4. External memory drives during reads, and the CPU can drive during writes while DBE is high.
30	D3 Bidirectional	Bidirectional	Data bit 3. External memory drives during reads, and the CPU can drive during writes while DBE is high.
31	D2 Bidirectional	Bidirectional	Data bit 2. External memory drives during reads, and the CPU can drive during writes while DBE is high.
32	D1 Bidirectional	Bidirectional	Data bit 1. External memory drives during reads, and the CPU can drive during writes while DBE is high.
33	D0 Bidirectional	Bidirectional	Data bit 0. External memory drives during reads, and the CPU can drive during writes while DBE is high.
34	R/W Output	Output	High for read and low for write. Goes high-impedance during HALT or TSC bus release.
35	NC None	None	Leave this contact unconnected.
36	DBE Input	Input	High permits the CPU to drive data during writes. Low makes the data outputs high-impedance. Normally driven by Φ2.
37	Φ2 Input	Input	Phase two of an external non-overlapping two-phase clock. It can present up to 70 pF. Drive DBE with this phase for normal bus operation.
38	NC None	None	Leave this contact unconnected.
39	TSC Input	Input	High puts address and R/W into high impedance. The timing diagram requires a short, timed clock pause. Keep low in a single-master system.
40	/RESET Input	Input	Active low. After power stabilizes, hold low for at least eight clock cycles. The reset vector is 0xFFFE high byte, then 0xFFFF low byte.

Signal assignments

Memory and peripheral bus

Use the full address and data buses with VMA, R/W and Φ2. On a normal write, DBE follows Φ2 to enable the CPU data drivers.

Two-phase clock

The external clock driver must supply both non-overlapping phases and their different capacitive loads.

Interrupts and reset

IRQ is maskable and level-sensitive, NMI is edge-triggered, and reset starts from the vector at 0xFFFE–0xFFFF.

Halt and bus ownership

HALT and BA provide the halted-bus handshake. TSC and DBE independently control address and data drivers for externally timed bus takeover.

Electrical limits

Parameter	Limit	Conditions and source
Operating supply4.75–5.25 V	4.75–5.25 V	VCC relative to VSS. Motorola MC6800 data sheet DS9471-R2, p. 2
Logic input levelsLOW ≤ 0.8 V, HIGH ≥ 2.0 V	LOW ≤ 0.8 V, HIGH ≥ 2.0 V	Logic inputs excluding the two clock pins. Motorola MC6800 data sheet DS9471-R2, p. 2
Clock input levelsLOW ≤ 0.4 V, HIGH ≥ VCC − 0.6 V	LOW ≤ 0.4 V, HIGH ≥ VCC − 0.6 V	Φ1 and Φ2 at the IC, with up to 35 pF and 70 pF input capacitance respectively. Motorola MC6800 data sheet DS9471-R2, pp. 2–3
Logic output levelsLOW ≤ 0.4 V at 1.6 mA, HIGH ≥ 2.4 V	LOW ≤ 0.4 V at 1.6 mA, HIGH ≥ 2.4 V	At minimum VCC. HIGH sourcing loads are 205 µA for data, 145 µA for address/R/W/VMA and 100 µA for BA. Motorola MC6800 data sheet DS9471-R2, p. 2
Clock frequency100 kHz minimum, 1 / 1.5 / 2 MHz maximum	100 kHz minimum, 1 / 1.5 / 2 MHz maximum	Maximum by grade. Check both phase widths, total up time and overlap at the specified measurement thresholds. Motorola MC6800 data sheet DS9471-R2, p. 3, Fig. 1
Absolute voltage limits−0.3 to +7.0 V	−0.3 to +7.0 V	VCC and input stress limits relative to VSS. Use the operating values for circuit design. Motorola MC6800 data sheet DS9471-R2, p. 2

Models and documents

Covers MC6800, MC68A00 and MC68B00 as documented in DS9471-R2. The MC6802 and MC6808 use different pin assignments. The term “6800 interface” on a display refers to its host bus protocol and has a module-specific pinout.

MC6800: 1.0 MHz maximum. MC6800P/S/L (0–70 °C) and MC6800CP/CS/CL (−40 to +85 °C).
MC68A00: 1.5 MHz maximum. MC68A00P/S/L (0–70 °C) and MC68A00CP/CS/CL (−40 to +85 °C).
MC68B00: 2.0 MHz maximum. MC68B00P/S/L (0–70 °C) in DS9471-R2.

Motorola MC6800 data sheet DS9471-R2· Manufacturer scan, © 1984. Pin and order tables on p. 1, DC characteristics and clocks on pp. 2–3, bus and reset on pp. 7–10. Scan SHA-256 fc7785e1b7ad01b55679fec5673814f5df60df0ae63fb063accbfb6827fc55b8.
Motorola Microcontroller and Microprocessor Families, Vol. 1 (1988)· Manufacturer data book. Consult separate sections for MC6802 and MC6808.