Motorola MC6809 pinout

HMOS 8-bit MPU with a 16-bit address bus, three hardware interrupt inputs and external RAM and ROM. Choose the pin map by the part marking and clock arrangement.

MC6809 DIP-40

40 contacts Current package

MC6809E DIP-40 40 contacts

Motorola · Motorola P plastic (Case 711), S CERDIP (Case 734) and L ceramic (Case 715) share this top-view 40-pin assignment. On-chip oscillator.

1.5 MHz maximum bus rate. MC68A09P/S/L (0–70 °C) and MC68A09CP/CS/CL (−40 to +85 °C).

MC6809 DIP-40 pinout

Top view · Pin 1 at upper left · Schematic outline

Selected pin details

10 · A2

Output · Outputs

Address bit 2. Valid at the rising edge of Q in a normal bus cycle. This line is three-state capable.

Motorola MC6809 datasheet DS9845-R2, pin assignment and pin descriptions

Electrical limits · Link to this pin

All 40 pins

Pin	Signal	Direction	Function
1	VSS Supply return	Supply return	Reference and supply return. Connect to the 0 V rail.
2	/NMI Input	Input	Falling-edge nonmaskable request. Inhibited after reset until software initializes the hardware stack pointer.
3	/IRQ Input	Input	Active-low level-sensitive interrupt controlled by the I flag. IRQ stacks the full processor state.
4	/FIRQ Input	Input	Active-low level-sensitive fast interrupt controlled by the F flag. FIRQ stacks the program counter and condition codes.
5	BS Output	Output	Bus status. Interpret with BA to distinguish normal execution, interrupt acknowledge, SYNC acknowledge and halt/bus grant.
6	BA Output	Output	Bus available. Interpret with BS and the timing table before granting another driver access to the bus.
7	VCC Supply	Supply	Regulated 5 V supply. Decouple to VSS close to the package.
8	A0 Output	Output	Address bit 0. Valid at the rising edge of Q in a normal bus cycle. This line is three-state capable.
9	A1 Output	Output	Address bit 1. Valid at the rising edge of Q in a normal bus cycle. This line is three-state capable.
10	A2 Output	Output	Address bit 2. Valid at the rising edge of Q in a normal bus cycle. This line is three-state capable.
11	A3 Output	Output	Address bit 3. Valid at the rising edge of Q in a normal bus cycle. This line is three-state capable.
12	A4 Output	Output	Address bit 4. Valid at the rising edge of Q in a normal bus cycle. This line is three-state capable.
13	A5 Output	Output	Address bit 5. Valid at the rising edge of Q in a normal bus cycle. This line is three-state capable.
14	A6 Output	Output	Address bit 6. Valid at the rising edge of Q in a normal bus cycle. This line is three-state capable.
15	A7 Output	Output	Address bit 7. Valid at the rising edge of Q in a normal bus cycle. This line is three-state capable.
16	A8 Output	Output	Address bit 8. Valid at the rising edge of Q in a normal bus cycle. This line is three-state capable.
17	A9 Output	Output	Address bit 9. Valid at the rising edge of Q in a normal bus cycle. This line is three-state capable.
18	A10 Output	Output	Address bit 10. Valid at the rising edge of Q in a normal bus cycle. This line is three-state capable.
19	A11 Output	Output	Address bit 11. Valid at the rising edge of Q in a normal bus cycle. This line is three-state capable.
20	A12 Output	Output	Address bit 12. Valid at the rising edge of Q in a normal bus cycle. This line is three-state capable.
21	A13 Output	Output	Address bit 13. Valid at the rising edge of Q in a normal bus cycle. This line is three-state capable.
22	A14 Output	Output	Address bit 14. Valid at the rising edge of Q in a normal bus cycle. This line is three-state capable.
23	A15 Output	Output	Address bit 15. Valid at the rising edge of Q in a normal bus cycle. This line is three-state capable.
24	D7 Bidirectional	Bidirectional	Data bit 7. Driven by external memory on reads and the MPU on writes. Meet the setup and hold times around E.
25	D6 Bidirectional	Bidirectional	Data bit 6. Driven by external memory on reads and the MPU on writes. Meet the setup and hold times around E.
26	D5 Bidirectional	Bidirectional	Data bit 5. Driven by external memory on reads and the MPU on writes. Meet the setup and hold times around E.
27	D4 Bidirectional	Bidirectional	Data bit 4. Driven by external memory on reads and the MPU on writes. Meet the setup and hold times around E.
28	D3 Bidirectional	Bidirectional	Data bit 3. Driven by external memory on reads and the MPU on writes. Meet the setup and hold times around E.
29	D2 Bidirectional	Bidirectional	Data bit 2. Driven by external memory on reads and the MPU on writes. Meet the setup and hold times around E.
30	D1 Bidirectional	Bidirectional	Data bit 1. Driven by external memory on reads and the MPU on writes. Meet the setup and hold times around E.
31	D0 Bidirectional	Bidirectional	Data bit 0. Driven by external memory on reads and the MPU on writes. Meet the setup and hold times around E.
32	R/W Output	Output	High for read and low for write. Qualify memory strobes with the clock and bus control for the exact CPU variant.
33	/DMA/BREQ Input	Input	Low requests temporary bus ownership. Observe BA and BS and allow for automatic CPU self-refresh cycles. Keep high when unused.
34	E Output	Output	Bus timing output. The falling edge latches read data. E runs at one quarter of the oscillator frequency.
35	Q Output	Output	Quadrature clock output. Q leads E, and the address is valid at the rising edge of Q.
36	MRDY Input	Input	High allows normal cycle timing. Low can stretch a valid memory cycle. Check early-mask synchronization restrictions.
37	/RESET Input	Input	Active-low Schmitt-trigger reset. Needs at least 4.0 V to release. The CPU reads the reset entry point high byte at 0xFFFE, then low byte at 0xFFFF.
38	EXTAL Input	Input	Crystal terminal or TTL-compatible external time-base input. For an external driver, ground XTAL and drive this pin at four times the bus clock.
39	XTAL Oscillator terminal	Oscillator terminal	Crystal terminal. Connect to ground when using an external logic source on EXTAL.
40	/HALT Input	Input	Low pauses after the current instruction. BA and BS go high and the CPU releases the bus. Keep both clocks running.

Signal assignments

External memory bus

The processor drives 16 address lines and reads or writes 8 data lines. Address is valid at Q rising, and read data latches at E falling.

Oscillator and bus clocks

A crystal across EXTAL and XTAL, or an external clock on EXTAL with XTAL grounded, supplies the 4× time base. E and Q are divided bus clock outputs.

Interrupts and reset

IRQ and FIRQ are level-sensitive and maskable. NMI is edge-sensitive and enabled after stack initialization. RESET has its own input threshold.

Bus ownership and wait states

HALT or DMA/BREQ can release the bus. MRDY can stretch valid memory cycles. Check the documented timing restrictions before applying either mode.

Electrical limits

Parameter	Limit	Conditions and source
Operating supply4.75–5.25 V	4.75–5.25 V	VCC relative to VSS. Motorola MC6809 datasheet DS9845-R2, DC characteristics
RESET levelsLOW ≤ 0.8 V, HIGH ≥ 4.0 V	LOW ≤ 0.8 V, HIGH ≥ 4.0 V	Active-low Schmitt-trigger input. Check the driver high against the RESET threshold at the CPU. Motorola MC6809 datasheet DS9845-R2, DC characteristics
Logic and EXTAL inputsLOW ≤ 0.8 V, HIGH ≥ 2.0 V	LOW ≤ 0.8 V, HIGH ≥ 2.0 V	General logic inputs and EXTAL in driven logic mode. RESET has a higher HIGH requirement. Motorola MC6809 datasheet DS9845-R2, DC characteristics
Logic output levelsLOW ≤ 0.5 V at 2 mA, HIGH ≥ 2.4 V	LOW ≤ 0.5 V at 2 mA, HIGH ≥ 2.4 V	At minimum VCC. HIGH sourcing loads are 205 µA for data, 145 µA for address/R/W/Q/E and 100 µA for BA/BS. Motorola MC6809 datasheet DS9845-R2, DC characteristics
Crystal or EXTAL rate0.4 MHz minimum, 4 / 6 / 8 MHz maximum	0.4 MHz minimum, 4 / 6 / 8 MHz maximum	Maximum by grade. E and Q run at one quarter of this rate in unstretched cycles. Motorola MC6809 datasheet DS9845-R2, DC characteristics and Fig. 11
Absolute voltage limits−0.3 to +7.0 V	−0.3 to +7.0 V	VCC and input stress limits relative to VSS. Use the operating values for circuit design. Motorola MC6809 datasheet DS9845-R2, maximum ratings

Models and documents

Covers the Motorola MC6809 and MC6809E plus their A and B speed grades. On the MC6809, E and Q are outputs. On the MC6809E, both are inputs, and pins 33, 36, 38 and 39 also differ. Hitachi HD6309 and later CMOS versions require their own datasheets.

MC6809: 1.0 MHz maximum bus rate. MC6809P/S/L (0–70 °C) and MC6809CP/CS/CL (−40 to +85 °C).
MC68A09: 1.5 MHz maximum bus rate. MC68A09P/S/L (0–70 °C) and MC68A09CP/CS/CL (−40 to +85 °C).
MC68B09: 2.0 MHz maximum bus rate. MC68B09P/S/L (0–70 °C) and MC68B09CP/CS/CL (−40 to +85 °C).

Motorola MC6809 datasheet DS9845-R2· Manufacturer scan, © 1983. Pin map p. 1, electrical and bus timing pp. 2–3, crystal and reset pp. 7–8, ordering p. 35. Scan SHA-256 87037123596de83bbc44ac63fbcde3950d368d5ee30880bffaa54e23bb81ea68.
Motorola MC6809E datasheet DS9846-R2· Manufacturer scan, © 1984. Check the pin assignment, external clock thresholds and timing, TSC timing and ordering table. Scan SHA-256 42c50598f2184bc37535a8d59be60a895c14e34919d706317b18f02f73441808.
Motorola MC6809–MC6809E Microprocessor Programming Manual· Programming model, interrupt handling and vectors. Appendix B lists the two pin assignments side by side.