Spark Logic

7474 dual D flip-flop connection guide

7474 dual D flip-flop SOIC-14 wiring guide with power, signal assignments, and bench checks.

PDIP-14 14 contacts

SOIC-14

14 contacts Current package

Texas Instruments · TI package D · 1.27 mm lead pitch · 14-pin D/N top-view assignment in SDLS119 p. 1 and historical SOIC order code in the packaging addendum.

Power and bypass

Required

Wire the regulated supply and its return with power off. Fit a 100 nF ceramic capacitor close to the package. Complete the chosen signal circuit before turning on power.

C1 100 nF between Regulated +5 V and GroundRegulated +5 VC1 100 nFGround

Bench checks

  • Verify 4.75–5.25 V from pin 14 to pin 7. Use the same ground for the driver and probe.

TI SDLS119, March 1988 revision, pp. 1 and 4. C1 is a local decoupling design choice.

Connection scenarios

Divide a clock by two

Connect 1Q# back to 1D. Keep PRE# HIGH and clear the flip-flop before starting a clean 1 kHz, 50% duty-cycle test clock. Leave 2Q and 2Q# open.

Bench checks

  • Verify CLK at 1 kHz and Q at 500 Hz. Verify the feedback stays stable for at least 5 ns after CLK↑ on the fitted part. The datasheet does not guarantee a minimum clock-to-output delay for a direct feedback loop.
  • The single D load draws up to 1.6 mA LOW and 40 µA HIGH, within the Q# output drive. At 5 V and 25 °C the datasheet lists up to 40 ns CLK-to-output delay with its specified test load.

TI SDLS119, March 1988 revision, pp. 1 and 4.

SOIC-14 wiring map

Highlighted contacts are used in the required step or selected circuit. Select a contact to inspect it.

Top view · Pin 1 at upper left · Schematic outline
Selected pin details

5 · 1Q

Output · Outputs

Non-inverting stored output. A power-up state is unspecified until an asynchronous control or a valid clock edge sets it.

TI SDLS119, March 1988 revision, p. 1

Electrical limits · Pin in the reference

Models and documents

Standard commercial SN7474 TTL. Use the separate datasheet columns for military SN5474, low-power Schottky SN74LS74A or Schottky SN74S74. A CMOS 74HC74 or 74HCT74 has its own electrical and timing limits.

SN7474DR
Historical 14-pin SOIC tape-and-reel order code, listed as obsolete in the archived TI addendum.