Intel 80286 pinout

Pinout and board bring-up for Intel’s 16-bit HMOS 80286, with a 24-bit physical address bus, a separate 16-bit data bus and a protected mode.

LCC-68

68 contacts Current package

PGA-68 68 contacts

PLCC-68 68 contacts

Intel · Leadless chip carrier with 17 contacts per edge. Component-side view, pin 1 at the lower-left end of the bottom edge. See Intel 210253-013, p. 3-2, Fig. 2.

LCC-68 pinout

LCC-68

Top view · pin 1 at lower left Scroll the map to reach all contacts.

Selected pin details

1 · BHE#

Output · Control

Low selects the high byte lane D15–D8. A0 low selects the low lane. High during RESET.

Intel 210253-013, p. 3-2, Fig. 2; Intel 210253-013, Table 1

Electrical limits · Link to this pin

All 68 pins

Pin	Signal	Direction	Function
1	BHE# Output	Output	Low selects the high byte lane D15–D8. A0 low selects the low lane. High during RESET.
2	NC No connection	No connection	Leave this contact electrically open.
3	NC No connection	No connection	Leave this contact electrically open.
4	S1# Output	Output	Bus status bit 1. Decode with S0#, M/IO# and COD/INTA#. High during RESET.
5	S0# Output	Output	Bus status bit 0. Decode with S1#, M/IO# and COD/INTA#. High during RESET.
6	PEACK# Output	Output	Active-low processor extension acknowledge. High during RESET.
7	A23 Output	Output	Physical address bit. High during RESET and high impedance when the CPU grants the bus.
8	A22 Output	Output	Physical address bit. High during RESET and high impedance when the CPU grants the bus.
9	VSS Supply return	Supply return	Connect all three VSS contacts to the same low-impedance ground.
10	A21 Output	Output	Physical address bit. High during RESET and high impedance when the CPU grants the bus.
11	A20 Output	Output	Physical address bit. High during RESET and high impedance when the CPU grants the bus.
12	A19 Output	Output	Physical address bit. High during RESET and high impedance when the CPU grants the bus.
13	A18 Output	Output	Physical address bit. High during RESET and high impedance when the CPU grants the bus.
14	A17 Output	Output	Physical address bit. High during RESET and high impedance when the CPU grants the bus.
15	A16 Output	Output	Physical address bit. High during RESET and high impedance when the CPU grants the bus.
16	A15 Output	Output	Physical address bit. High during RESET and high impedance when the CPU grants the bus.
17	A14 Output	Output	Physical address bit. High during RESET and high impedance when the CPU grants the bus.
18	A13 Output	Output	Physical address bit. High during RESET and high impedance when the CPU grants the bus.
19	A12 Output	Output	Physical address bit. High during RESET and high impedance when the CPU grants the bus.
20	A11 Output	Output	Physical address bit. High during RESET and high impedance when the CPU grants the bus.
21	A10 Output	Output	Physical address bit. High during RESET and high impedance when the CPU grants the bus.
22	A9 Output	Output	Physical address bit. High during RESET and high impedance when the CPU grants the bus.
23	A8 Output	Output	Physical address bit. High during RESET and high impedance when the CPU grants the bus.
24	A7 Output	Output	Physical address bit. High during RESET and high impedance when the CPU grants the bus.
25	A6 Output	Output	Physical address bit. High during RESET and high impedance when the CPU grants the bus.
26	A5 Output	Output	Physical address bit. High during RESET and high impedance when the CPU grants the bus.
27	A4 Output	Output	Physical address bit. High during RESET and high impedance when the CPU grants the bus.
28	A3 Output	Output	Physical address bit. High during RESET and high impedance when the CPU grants the bus.
29	RESET Input	Input	Active high. Release low in sync with CLK. The first memory fetch is at physical address FFFFF0h.
30	VCC Supply input	Supply input	Connect both VCC contacts to the regulated +5 V rail and place the bypass capacitor close to the socket.
31	CLK Input	Input	Drive at twice the CPU rate using an 82C284 or an equivalent qualified clock circuit. CLK has separate input thresholds.
32	A2 Output	Output	Physical address bit. High during RESET and high impedance when the CPU grants the bus.
33	A1 Output	Output	Physical address bit. High during RESET and high impedance when the CPU grants the bus.
34	A0 Output	Output	Physical address bit. High during RESET and high impedance when the CPU grants the bus.
35	VSS Supply return	Supply return	Connect all three VSS contacts to the same low-impedance ground.
36	D0 Bidirectional	Bidirectional	Data bus bit. High impedance during RESET and when another master owns the bus.
37	D8 Bidirectional	Bidirectional	Data bus bit. High impedance during RESET and when another master owns the bus.
38	D1 Bidirectional	Bidirectional	Data bus bit. High impedance during RESET and when another master owns the bus.
39	D9 Bidirectional	Bidirectional	Data bus bit. High impedance during RESET and when another master owns the bus.
40	D2 Bidirectional	Bidirectional	Data bus bit. High impedance during RESET and when another master owns the bus.
41	D10 Bidirectional	Bidirectional	Data bus bit. High impedance during RESET and when another master owns the bus.
42	D3 Bidirectional	Bidirectional	Data bus bit. High impedance during RESET and when another master owns the bus.
43	D11 Bidirectional	Bidirectional	Data bus bit. High impedance during RESET and when another master owns the bus.
44	D4 Bidirectional	Bidirectional	Data bus bit. High impedance during RESET and when another master owns the bus.
45	D12 Bidirectional	Bidirectional	Data bus bit. High impedance during RESET and when another master owns the bus.
46	D5 Bidirectional	Bidirectional	Data bus bit. High impedance during RESET and when another master owns the bus.
47	D13 Bidirectional	Bidirectional	Data bus bit. High impedance during RESET and when another master owns the bus.
48	D6 Bidirectional	Bidirectional	Data bus bit. High impedance during RESET and when another master owns the bus.
49	D14 Bidirectional	Bidirectional	Data bus bit. High impedance during RESET and when another master owns the bus.
50	D7 Bidirectional	Bidirectional	Data bus bit. High impedance during RESET and when another master owns the bus.
51	D15 Bidirectional	Bidirectional	Data bus bit. High impedance during RESET and when another master owns the bus.
52	CAP Bias filter node	Bias filter node	Connect a 47 nF ±20% capacitor rated for at least 12 V to VSS. Maximum DC leakage is 1 µA.
53	ERROR# Input	Input	Active-low numeric error indication from the 80287 coprocessor. Internal pull-up.
54	BUSY# Input	Input	Active-low busy indication from the 80287 coprocessor. Internal pull-up.
55	NC No connection	No connection	Leave this contact electrically open.
56	NC No connection	No connection	Leave this contact electrically open.
57	INTR Input	Input	Active-high maskable interrupt request. The CPU acknowledges it with a pair of bus cycles.
58	NC No connection	No connection	Leave this contact electrically open.
59	NMI Input	Input	Rising-edge non-maskable interrupt request. The CPU ignores it during internal reset.
60	VSS Supply return	Supply return	Connect all three VSS contacts to the same low-impedance ground.
61	PEREQ Input	Input	Active-high processor extension request from the 80287.
62	VCC Supply input	Supply input	Connect both VCC contacts to the regulated +5 V rail and place the bypass capacitor close to the socket.
63	READY# Input	Input	Low terminates the bus cycle when sampled at the proper clock phase. High inserts wait states.
64	HOLD Input	Input	Active-high request for another master to acquire the local bus. Wait for HLDA before the requesting device drives shared lines.
65	HLDA Output	Output	High grants the local bus in response to HOLD. Low during RESET when HOLD is low.
66	COD/INTA# Output	Output	Distinguishes instruction fetch and interrupt-acknowledge cycles as part of bus status. Low during RESET.
67	M/IO# Output	Output	Qualifies memory (high) or I/O (low) bus cycles. Low during RESET.
68	LOCK# Output	Output	Low identifies a locked bus sequence. External arbitration must preserve ownership. High during RESET.

Signal assignments

Local bus

The address and data buses are separate. A0 and BHE# select the byte lanes. An external bus controller decodes status into memory and I/O commands. READY# controls completion and wait states.

Clock and reset

An 82C284 can generate the clock and synchronize reset and ready to it. The CLK pin receives twice the CPU rate.

Interrupts

INTR is maskable and uses bus acknowledge cycles. NMI is edge-triggered and enters its fixed vector without an external acknowledge cycle.

Bus arbitration

A DMA or other bus master requests ownership with HOLD and waits for HLDA. Observe LOCK# when arbitrating shared resources.

80287 coprocessor

The 80287 uses dedicated request, acknowledge, busy and error lines plus the local data bus and decoded commands. See Intel Fig. 6-1 for the complete system and bus-buffer control.

Electrical limits

Parameter	Limit	Conditions and source
VCC operating range4.75–5.25 V	4.75–5.25 V	5 V ±5% relative to VSS. DC limits use case temperature from 0 to 85 °C. Intel 210253-013, p. 3-38 and Intel 210253-018, p. 2-99
Digital input low / high−0.5–0.8 V / 2.0 V to VCC + 0.5 V	−0.5–0.8 V / 2.0 V to VCC + 0.5 V	Relative to VSS, for inputs other than CLK. DC test at minimum operating frequency. Intel 210253-013, p. 3-38 and Intel 210253-018, p. 2-99
Digital output low / high≤ 0.45 V / ≥ 2.4 V	≤ 0.45 V / ≥ 2.4 V	Sinking 2.0 mA for low or sourcing 400 µA for high. DC test at minimum operating frequency. Intel 210253-013, p. 3-38 and Intel 210253-018, p. 2-99
CLK input low / high−0.5–0.6 V / 3.8 V to VCC + 0.5 V	−0.5–0.6 V / 3.8 V to VCC + 0.5 V	Relative to VSS. For edge timing, the AC test points are 1.0 V and 3.6 V. Intel 210253-013, p. 3-38 and Intel 210253-018, p. 2-99; Intel 210253-018, p. 2-100
CLK rise and fall time10 ns maximum (−8), 8 ns maximum (−10 and −12)	10 ns maximum (−8), 8 ns maximum (−10 and −12)	Measured between 1.0 V and 3.6 V. Use the fitted grade’s AC table for pulse widths and setup/hold timing. Intel 210253-018, p. 2-100
CLK frequency4 MHz minimum, twice CPU frequency	4 MHz minimum, twice CPU frequency	The HMOS core uses dynamic storage. Keep CLK running and use the AC table for the fitted speed grade. Intel 210760-002, pp. 3-27–3-29, Fig. 3-18
CAP substrate filter47 nF ±20%, 12 V, ≤ 1 µA leakage	47 nF ±20%, 12 V, ≤ 1 µA leakage	Connect from CAP to VSS. Hold RESET active while the bias circuit starts. Intel 210760-002, pp. 3-77–3-78, Fig. 3-73
RESET assertion5 ms startup plus 16 CPU cycles	5 ms startup plus 16 CPU cycles	Board-level power-up sequence from the hardware manual. Count from valid VCC and CLK, then release RESET in sync with CLK. Intel 210760-002, pp. 3-41–3-43 and 3-67–3-69

Models and documents

Covers the four Intel commercial HMOS speed grades listed in the September 1988 datasheet and the three package maps in its Fig. 2. Intel lists the grades and packages separately. Check the fitted part’s complete marking to identify its actual combination. System ROM, RAM, and I/O are external. Intel 80C286 and second-source parts have separate electrical specifications.

80286-6: 6 MHz CPU, 12 MHz CLK at rated speed. See Intel 210760-002 for 6 MHz local-bus timing examples.
80286-8: 8 MHz CPU, 16 MHz CLK.
80286-10: 10 MHz CPU, 20 MHz CLK.
80286-12: 12.5 MHz CPU, 25 MHz CLK.

Intel 80286 Hardware Reference Manual· Intel 210760-002 (1987). Ch. 3 and Fig. 3-72 cover the local bus and package maps. Fig. 3-73 covers supply and CAP. Fig. 6-1 shows the 80287 interface. Archive scan SHA-256 d3ece037a200b17ef32d78a055d0d96c3e47474d755d94569b9576a9a68c6915.
Intel 80286 datasheet (September 1988)· Intel 210253-013. Fig. 2 on p. 3-2 shows all three packages. Table 1 describes the pins. DC conditions are on p. 3-38. Scan SHA-256 36e1a8bf70272fcadf1163a55f02fcccaaf3e3dc73b9bd5c1ee1e8cc3229db1c.
Intel 80286 production datasheet (September 1993)· Intel 210253-018. Printed pp. 2-99–2-100 specify DC and AC conditions for the −8, −10, and −12 grades. The document footer identifies the revision. Scan SHA-256 afb8931d14de0834f1a70c2662e8ae27022b5b1c891edfa3d85704bccbafd595.