Intel 80286 connection guide
Intel 80286 PLCC-68 wiring guide with power, signal assignments, and bench checks.
Connect power and the bias capacitor
RequiredConnect both VCC pins and all three VSS pins. Put one low-impedance 100 nF bypass capacitor at the CPU socket. Use a separate 47 nF ±20% capacitor rated for at least 12 V with ≤ 1 µA leakage from CAP to VSS.
- +5 V
- VSS
- CAP filter
- CAP (52)
- C2.1
Bench checks
- With power off, check continuity from socket contacts 30 and 62 to the +5 V rail and from 9, 35 and 60 to ground.
- With the regulated supply on, measure 4.75–5.25 V at both VCC contacts relative to VSS.
- Confirm continuity from CAP contact 52 to the filter capacitor and from the other capacitor terminal to VSS with power off.
Intel 210760-002, pp. 3-77–3-78, Fig. 3-73
Connection scenarios
Trace the first ROM fetch
Probe the installed board after verifying power, CLK and RESET. Use labeled test pads or accessible latch and bus-controller pins. Choose 5 V-compatible high-impedance logic analyzer probes. These nets are measurement points on the existing circuit.
- Trigger
- RESET (29)
- Analyzer trigger input
- Memory cycle qualifier
- M/IO# (67)
- Analyzer channel 1
- Instruction cycle qualifier
- COD/INTA# (66)
- Analyzer channel 2
- Cycle start status 1
- S1# (4)
- Analyzer channel 3
- Cycle start status 0
- S0# (5)
- Analyzer channel 4
- Memory read command
- 82288 MRDC# output
- Analyzer channel 5
- ROM select
- Boot ROM chip select
- Analyzer channel 6
- Probe reference
Bench checks
- Trigger on the falling edge of RESET with the analyzer ground at board VSS. During the first instruction-read status phase expect M/IO# high, COD/INTA# high, S1# low and S0# high.
- Confirm the bus controller asserts MRDC# and the board decoder selects the boot ROM. If status appears without a read command, check the bus controller clock and enables. If the command appears without ROM select, check the address decode.
- To verify the physical address, repeat the capture with A23–A0. The CPU starts at FFFFF0h, so A23–A4 should be high and A3–A0 low in the first address-valid phase. ROM-side address lines may be latched or decoded by the board.
Intel 210760-002, Table 3-1 and pp. 3-67–3-70
PLCC-68 wiring map
29 · RESET
Active high. Release low in sync with CLK. The first memory fetch is at physical address FFFFF0h.
Models and documents
Covers the four Intel commercial HMOS speed grades listed in the September 1988 datasheet and the three package maps in its Fig. 2. Intel lists the grades and packages separately. Check the fitted part’s complete marking to identify its actual combination. System ROM, RAM, and I/O are external. Intel 80C286 and second-source parts have separate electrical specifications.
- 80286-6
- 6 MHz CPU, 12 MHz CLK at rated speed. See Intel 210760-002 for 6 MHz local-bus timing examples.
- 80286-8
- 8 MHz CPU, 16 MHz CLK.
- 80286-10
- 10 MHz CPU, 20 MHz CLK.
- 80286-12
- 12.5 MHz CPU, 25 MHz CLK.
- Intel 80286 Hardware Reference Manual· Intel 210760-002 (1987). Ch. 3 and Fig. 3-72 cover the local bus and package maps. Fig. 3-73 covers supply and CAP. Fig. 6-1 shows the 80287 interface. Archive scan SHA-256 d3ece037a200b17ef32d78a055d0d96c3e47474d755d94569b9576a9a68c6915.
- Intel 80286 datasheet (September 1988)· Intel 210253-013. Fig. 2 on p. 3-2 shows all three packages. Table 1 describes the pins. DC conditions are on p. 3-38. Scan SHA-256 36e1a8bf70272fcadf1163a55f02fcccaaf3e3dc73b9bd5c1ee1e8cc3229db1c.
- Intel 80286 production datasheet (September 1993)· Intel 210253-018. Printed pp. 2-99–2-100 specify DC and AC conditions for the −8, −10, and −12 grades. The document footer identifies the revision. Scan SHA-256 afb8931d14de0834f1a70c2662e8ae27022b5b1c891edfa3d85704bccbafd595.