Spark Logic

Intel 8051 connection guide

Intel 8051 DIP-40 wiring guide with power, signal assignments, and bench checks.

DIP-40

40 contacts Current package

Intel · Original dual-inline package shown in Intel’s original 8031/8051/8751 specification, Figure 3.

Power and internal code selection

Required

Power VCC from a regulated 5 V supply (±5%). Place a 100 nF ceramic bypass between VCC and VSS. The high strap on EA selects the installed mask ROM at reset address 0000h.

100 nF between VCC rail and GroundVCC rail100 nFGround

Bench checks

  • Confirm the package pin 1 mark before applying power and measure VCC relative to ground at the IC.
  • Use a 100 nF X7R capacitor rated at least 16 V as the local high-frequency bypass. Keep its loop short.
  • Confirm the on-chip mask ROM contains the intended startup code before selecting internal execution.

Intel MCS-51 User’s Manual (1981), pp. 6-1–6-4

Connection scenarios

Start the crystal oscillator

Use the original HMOS crystal configuration. Connect an 11.0592 MHz parallel-resonant crystal between XTAL1 and XTAL2, with one load capacitor from each pin to VSS.

Y1 11.0592 MHz between Oscillator input and Oscillator outputOscillator inputY1 11.0592 MHzOscillator output
C2 30 pF between Oscillator input and GroundOscillator inputC2 30 pFGround
C3 30 pF between Oscillator output and GroundOscillator outputC3 30 pFGround

Bench checks

  • For Y1, ECS-110.5-18-4XEN is rated for 18 pF load and 60 Ω maximum ESR. Two 30 pF C0G capacitors at ±5% contribute 15 pF nominal in series. With 3 pF assumed board and input stray capacitance, the total is 18 pF. Verify that assumption on the target board.
  • Keep both crystal traces and both capacitor returns short. Verify startup over the intended voltage and temperature range.
  • For external-drive troubleshooting, the later Intel HMOS guide places the signal on XTAL2 and grounds XTAL1. The preliminary original pin paragraph is less specific, so the crystal circuit is the covered bring-up example.

Intel MCS-51 Family User’s Manual (1994), chapter 3, pp. 3-31–3-32, Figures 30–32, and ECS HC-49USX ordering specifications

DIP-40 wiring map

Highlighted contacts are used in the required step or selected circuit. Select a contact to inspect it.

Top view. The notch is up, pin 1 is upper left and pin 40 is upper right.
Selected pin details

37 · P0.2

Bidirectional · Bidirectional

Open-drain GPIO. Latch 1 releases the output, so add an external pull-up when a driven HIGH is required. AD2 carries the multiplexed low address bit and data bit during external memory cycles, with an internal pull-up for bus operation.

After reset · Latch = 1. High impedance in GPIO mode.

Intel MCS-51, 1981 pp. 6-1–6-2 and 1994 pp. 3-6–3-7, 3-26–3-27

Electrical limits · Pin in the reference

Models and documents

This map covers the original Intel 8051 in the documented 40-pin DIP. Intel’s 8051AH, 80C51, ROMless 8031 and EPROM 8751 have their own electrical or programming specifications. The early original-device electrical table is marked preliminary.

Intel 8051
Original HMOS device, DIP-40. 4 KiB factory mask ROM, 128 B RAM, 32 port pins, two 16-bit timers, five interrupt sources and a full-duplex serial port.