Asynchronous UART
Fixed mapping. P3.0/RXD is input and P3.1/TXD is output. Set both P3 latch bits to 1. For mode 1 with reception enabled, set SCON = 50h and configure the baud generator before use.
Atmel AT89C52 pinout
Pinout, electrical limits and connections for the Atmel AT89C52, an MCS-51-compatible controller with 8 KiB Flash, 256 bytes of RAM and three 16-bit timer/counters.
Up to 24 MHz, 4.0–6.0 V. AT89C52-24PC: 0–70 °C. AT89C52-24PI: −40–85 °C. 8 KiB Flash and 256 B RAM.
PDIP-40 pinout
21 · P2.0
Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. Outputs A8 during external code fetches and 16-bit external data accesses. For MOVX @Ri it outputs the P2 latch value.
After reset · Latch = 1. Pulled HIGH when the pin is unloaded and used as GPIO.
All 40 pins
| Pin | Signal | Direction | Function |
|---|---|---|---|
| 1 | P1.0 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. T2 is the Timer 2 external count input or clock output in the corresponding Timer 2 mode. |
| 2 | P1.1 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. T2EX is the Timer 2 capture/reload trigger or up/down direction control in the corresponding Timer 2 mode. |
| 3 | P1.2 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. |
| 4 | P1.3 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. |
| 5 | P1.4 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. |
| 6 | P1.5 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. |
| 7 | P1.6 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. |
| 8 | P1.7 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. |
| 9 | RST Input | Input | Active-high reset. Hold HIGH for at least two machine cycles after the oscillator is running. A valid reset starts code at 0000h. |
| 10 | P3.0 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. RXD receives UART data in asynchronous modes and carries serial data in shift-register mode. Keep the corresponding latch bit at 1 for the alternate function. |
| 11 | P3.1 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. TXD sends UART data in asynchronous modes and supplies shift clock in mode 0. Keep the corresponding latch bit at 1 for the alternate function. |
| 12 | P3.2 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. INT0 accepts external interrupt 0 and can gate Timer 0. Keep the corresponding latch bit at 1 for the alternate function. |
| 13 | P3.3 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. INT1 accepts external interrupt 1 and can gate Timer 1. Keep the corresponding latch bit at 1 for the alternate function. |
| 14 | P3.4 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. T0 accepts external Timer 0 count pulses. Keep the corresponding latch bit at 1 for the alternate function. |
| 15 | P3.5 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. T1 accepts external Timer 1 count pulses. Keep the corresponding latch bit at 1 for the alternate function. |
| 16 | P3.6 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. /WR strobes writes to external data memory. Keep the corresponding latch bit at 1 for the alternate function. |
| 17 | P3.7 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. /RD strobes reads from external data memory. Keep the corresponding latch bit at 1 for the alternate function. |
| 18 | XTAL2 Output | Output | Oscillator-amplifier output. Leave unconnected when driving XTAL1 from an external clock. |
| 19 | XTAL1 Input | Input | Oscillator-amplifier input. Apply an external clock here when using the external-drive configuration. |
| 20 | GND Reference | Reference | Circuit ground and return for the supply, clock and logic signals. |
| 21 | P2.0 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. Outputs A8 during external code fetches and 16-bit external data accesses. For MOVX @Ri it outputs the P2 latch value. |
| 22 | P2.1 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. Outputs A9 during external code fetches and 16-bit external data accesses. For MOVX @Ri it outputs the P2 latch value. |
| 23 | P2.2 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. Outputs A10 during external code fetches and 16-bit external data accesses. For MOVX @Ri it outputs the P2 latch value. |
| 24 | P2.3 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. Outputs A11 during external code fetches and 16-bit external data accesses. For MOVX @Ri it outputs the P2 latch value. |
| 25 | P2.4 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. Outputs A12 during external code fetches and 16-bit external data accesses. For MOVX @Ri it outputs the P2 latch value. |
| 26 | P2.5 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. Outputs A13 during external code fetches and 16-bit external data accesses. For MOVX @Ri it outputs the P2 latch value. |
| 27 | P2.6 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. Outputs A14 during external code fetches and 16-bit external data accesses. For MOVX @Ri it outputs the P2 latch value. |
| 28 | P2.7 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. Outputs A15 during external code fetches and 16-bit external data accesses. For MOVX @Ri it outputs the P2 latch value. |
| 29 | PSEN Output | Output | Active-low external program-memory read strobe. It enables instruction bytes onto Port 0 during external fetches. |
| 30 | ALE Output | Output | Address Latch Enable (ALE/PROG). It strobes the low address byte into the external latch. Bit 0 at SFR 8Eh suppresses idle ALE pulses during internal execution. PROG is a separate Flash programming mode. |
| 31 | EA Input | Input | External Access (EA/VPP). Strap HIGH for internal Flash at 0000h–1FFFh or LOW for external code from 0000h. The 12 V programming level applies only to the documented programming mode. |
| 32 | P0.7 Bidirectional | Bidirectional | Open-drain GPIO. Latch 1 releases the output, so add an external pull-up when a driven HIGH is required. AD7 carries the multiplexed low address bit and data bit during external memory cycles, with an internal pull-up for bus operation. |
| 33 | P0.6 Bidirectional | Bidirectional | Open-drain GPIO. Latch 1 releases the output, so add an external pull-up when a driven HIGH is required. AD6 carries the multiplexed low address bit and data bit during external memory cycles, with an internal pull-up for bus operation. |
| 34 | P0.5 Bidirectional | Bidirectional | Open-drain GPIO. Latch 1 releases the output, so add an external pull-up when a driven HIGH is required. AD5 carries the multiplexed low address bit and data bit during external memory cycles, with an internal pull-up for bus operation. |
| 35 | P0.4 Bidirectional | Bidirectional | Open-drain GPIO. Latch 1 releases the output, so add an external pull-up when a driven HIGH is required. AD4 carries the multiplexed low address bit and data bit during external memory cycles, with an internal pull-up for bus operation. |
| 36 | P0.3 Bidirectional | Bidirectional | Open-drain GPIO. Latch 1 releases the output, so add an external pull-up when a driven HIGH is required. AD3 carries the multiplexed low address bit and data bit during external memory cycles, with an internal pull-up for bus operation. |
| 37 | P0.2 Bidirectional | Bidirectional | Open-drain GPIO. Latch 1 releases the output, so add an external pull-up when a driven HIGH is required. AD2 carries the multiplexed low address bit and data bit during external memory cycles, with an internal pull-up for bus operation. |
| 38 | P0.1 Bidirectional | Bidirectional | Open-drain GPIO. Latch 1 releases the output, so add an external pull-up when a driven HIGH is required. AD1 carries the multiplexed low address bit and data bit during external memory cycles, with an internal pull-up for bus operation. |
| 39 | P0.0 Bidirectional | Bidirectional | Open-drain GPIO. Latch 1 releases the output, so add an external pull-up when a driven HIGH is required. AD0 carries the multiplexed low address bit and data bit during external memory cycles, with an internal pull-up for bus operation. |
| 40 | VCC Supply | Supply | Connect to the regulated positive supply. Place the bypass capacitor close to VCC and ground. |
Signal assignments
Synchronous serial
Fixed mapping. In serial mode 0, RXD is bidirectional shift data and TXD outputs the shift clock. Set SM0 = 0 and SM1 = 0 in SCON, and leave both P3 latch bits at 1.
External interrupts
P3.2/INT0 and P3.3/INT1 are independent active-low inputs. Keep both latch bits high. IT0 and IT1 in TCON select low-level (0) or falling-edge (1) operation. Set the respective EX bit and global EA in IE to enable the interrupt.
Timer 0 and 1 inputs
P3.4/T0 and P3.5/T1 accept external counts when the respective C/T bit in TMOD is 1. The corresponding INT pin is a separate gate input when GATE is set. Keep each used port latch bit at 1.
External program memory
P0 outputs A0–A7 and then receives D0–D7. P2 outputs A8–A15. Latch the low address with ALE and use /PSEN as the external code read strobe. Strap EA low to start at external address 0000h. The bus occupies P0 and P2 during code fetches.
External data memory
P0 carries the low address and bidirectional data. Use ALE for the low-address latch and P3.7/RD and P3.6/WR for data strobes. P2 outputs the high address for MOVX @DPTR or its latch value for MOVX @Ri.
Timer 2
P1.0/T2 is the external counter input when T2CON.C/T2 = 1. In clock-output mode it is the output when T2MOD.T2OE = 1 and C/T2 = 0. P1.1/T2EX can trigger capture or reload when enabled, or control the direction in up/down mode.
Parallel Flash programming
P1 carries A0–A7 and P2.0–P2.4 carry A8–A12. P0 carries the data byte. P2.6, P2.7, P3.6 and P3.7 select programming or verify mode with RST high and PSEN low. ALE/PROG receives the write pulse and P3.4 reports ready/busy. Match the EA/VPP mode to the actual top-side marking and signature in the datasheet.
Electrical limits
| Parameter | Limit | Conditions and source |
|---|---|---|
| VCC operating range4.0–6.0 V | 4.0–6.0 V | Referenced to GND. Commercial codes are specified at 0–70 °C, industrial codes at −40–85 °C. Atmel AT89C52, 0313H–02/00, pp. 17, 22 |
| Oscillator frequency0 Hz to marked speed grade | 0 Hz to marked speed grade | 12, 16, 20 or 24 MHz maximum depending on ordering code. Clock stopped at 0 Hz cannot advance the reset sequencer. Atmel AT89C52, 0313H–02/00, pp. 1, 20, 22 |
| Digital inputsVIL ≤ 0.2 × VCC − 0.1 V, VIH ≥ 0.2 × VCC + 0.9 V | VIL ≤ 0.2 × VCC − 0.1 V, VIH ≥ 0.2 × VCC + 0.9 V | General digital pins. For EA, VIL ≤ 0.2 × VCC − 0.3 V. For XTAL1 and RST, VIH ≥ 0.7 × VCC. Atmel AT89C52, 0313H–02/00, p. 17 |
| Output LOW≤ 0.45 V | ≤ 0.45 V | At 1.6 mA sink for P1–P3 and 3.2 mA for P0, ALE and PSEN. Larger loads can raise VOL. Atmel AT89C52, 0313H–02/00, p. 17 |
| Output HIGH≥ 2.4 V | ≥ 2.4 V | VCC = 4.5–5.5 V. At 60 µA source for P1–P3, ALE and PSEN. At 800 µA for P0 in external-bus mode. P0 GPIO HIGH is set by its external pull-up. Atmel AT89C52, 0313H–02/00, p. 17 |
| Steady-state sink current ceilings10 mA/pin, 26 mA P0, 15 mA each P1–P3, 71 mA total | 10 mA/pin, 26 mA P0, 15 mA each P1–P3, 71 mA total | Design for the lower VOL test currents when the specified logic LOW is required. Atmel AT89C52, 0313H–02/00, p. 17 note 1 |
| ResetRST HIGH for ≥ 24 oscillator periods | RST HIGH for ≥ 24 oscillator periods | After the clock is running. PC restarts at 0000h, port latches become FFh. RST has a 50–300 kΩ internal pulldown. Atmel AT89C52, 0313H–02/00, pp. 3–4, 17 |
| Active supply current25 mA maximum | 25 mA maximum | At 12 MHz, DC characteristics. Budget separately for external loads and oscillator circuitry. Atmel AT89C52, 0313H–02/00, p. 17 |
Models and documents
This reference resolves the abbreviated 89C52 name to Atmel’s AT89C52, document 0313H. It covers all four package drawings and the listed 12/16/20/24 MHz speed grades. Check the full marking on parts from other manufacturers. The AT89S52 uses its own programming interface and datasheet.
- AT89C52-12
- Up to 12 MHz, 4.0–6.0 V. AT89C52-12PC: 0–70 °C. AT89C52-12PI: −40–85 °C. 8 KiB Flash and 256 B RAM.
- AT89C52-16
- Up to 16 MHz, 4.0–6.0 V. AT89C52-16PC: 0–70 °C. AT89C52-16PI: −40–85 °C. 8 KiB Flash and 256 B RAM.
- AT89C52-20
- Up to 20 MHz, 4.0–6.0 V. AT89C52-20PC: 0–70 °C. AT89C52-20PI: −40–85 °C. 8 KiB Flash and 256 B RAM.
- AT89C52-24
- Up to 24 MHz, 4.0–6.0 V. AT89C52-24PC: 0–70 °C. AT89C52-24PI: −40–85 °C. 8 KiB Flash and 256 B RAM.
- Datasheet for AT89C52· Atmel 0313H–02/00, February 2000. Pin configurations p. 1, pin descriptions pp. 3–4, SFR reset p. 5, Timer 2 pp. 6–10, oscillator p. 12, DC p. 17, clock drive p. 20, ordering and package drawings pp. 22–23. SHA-256 f8d392b5cc25322766180e74d323b5c8abd647c98f9d4fbfc6f99a7d1f89e4bd.
- Intel MCS-51 Family User’s Manual· Intel 272383-002, February 1994, chapter 3. Core operation, port latches and serial interface. The AT89C52 datasheet governs its own electrical limits and Timer 2 extensions.