Spark Logic

AT91SAM7X connection guide

AT91SAM7X LQFP-100 wiring guide with power, signal assignments, and bench checks.

LQFP-100

100 contacts Current package
TFBGA-100 100 contacts

Microchip Technology · LQFP-100 · Quad flat package · Refer to the mechanical drawing for footprint dimensions.

512 KiB flash · 128 KiB SRAM · industrial −40 to +85 °C.

Power from the on-chip 1.8 V regulator

Required

Use a current-limited 3.3 V supply and the internal regulator. Connect VDDOUT to the core and PLL supplies and decouple every supply pin. Connect all GND contacts to the same ground plane.

4.7 µF + 100 nF at VDDIN and 100 nF per VDDIO and VDDFLASH supply between 3.3 V rail and Ground3.3 V rail4.7 µF + 100 nF at VDDIN and 100 nF per VDDIO and VDDFLASH supplyGround
2.2 µF + 100 nF at VDDOUT and 100 nF per core/PLL supply between 1.8 V rail and Ground1.8 V rail2.2 µF + 100 nF at VDDOUT and 100 nF per core/PLL supplyGround

Bench checks

  • Verify each supply and ground contact against the selected package. Check that the VDDIN rise meets the manufacturer’s minimum 6 V/ms before relying on regulator startup.
  • Verify that VDDOUT settles near 1.8 V. The power-only circuit straps unused dedicated ADC inputs, reference, and USB signals as in the hardware checklist. Leave any USB cable disconnected and disable the unused USB transceiver.
  • Leave XIN, XOUT and PLLRC unused for the internal slow-clock debug fixture. Add the selected clock and loop-filter circuits before switching the firmware to the main clock or PLL.

6260C §3 and 6120K §§5, 7, 24–25

Connection scenarios

Connect a JTAG probe

Start with the 3.3 V fixture. Use a JTAG probe that supports ARM7TDMI with target-reference sensing. Keep JTAGSEL low for ICE debugging.

100 kΩ between Target I/O voltage and Test clockTarget I/O voltage100 kΩTest clock
100 kΩ between Target I/O voltage and Test mode selectTarget I/O voltage100 kΩTest mode select
100 kΩ between Target I/O voltage and Data to targetTarget I/O voltage100 kΩData to target

Bench checks

  • Start with a low JTAG clock. Confirm the probe can detect the chain before configuring a faster system clock.
  • Check that the probe and target have a common ground and that the probe sees 3.3 V at its reference input.

6260C §3, ICE and JTAG, and 6120K §8

LQFP-100 wiring map

Highlighted contacts are used in the required step or selected circuit. Select a contact to inspect it.

LQFP-100
Top view · Pin 1 at the upper left · Schematic outline Scroll the map to reach all contacts.
Selected pin details

15 · VDDCORE

Supply · Power

1.8 V supply for the core and embedded logic. Connect all core supply contacts.

6120K · Package pinout and signal descriptions

Electrical limits · Pin in the reference

Models and documents

Includes SAM7X128, SAM7X256 and SAM7X512 across the LQFP and TFBGA maps. Select the marked ordering code for the flash size and use the matching silicon errata.

AT91SAM7X512
512 KiB flash · 128 KiB SRAM
AT91SAM7X512-AU
512 KiB flash · 128 KiB SRAM · industrial −40 to +85 °C.
AT91SAM7X512B-AU
512 KiB flash · 128 KiB SRAM · industrial −40 to +85 °C.
AT91SAM7X512B-AUR
512 KiB flash · 128 KiB SRAM · industrial −40 to +85 °C · tape and reel.
AT91SAM7X256
256 KiB flash · 64 KiB SRAM
AT91SAM7X256-AU
256 KiB flash · 64 KiB SRAM · industrial −40 to +85 °C.
AT91SAM7X256B-AU
256 KiB flash · 64 KiB SRAM · industrial −40 to +85 °C.
AT91SAM7X256C-AU
256 KiB flash · 64 KiB SRAM · industrial −40 to +85 °C.
AT91SAM7X128
128 KiB flash · 32 KiB SRAM
AT91SAM7X128-AU
128 KiB flash · 32 KiB SRAM · industrial −40 to +85 °C.
AT91SAM7X128B-AU
128 KiB flash · 32 KiB SRAM · industrial −40 to +85 °C.
AT91SAM7X128C-AU
128 KiB flash · 32 KiB SRAM · industrial −40 to +85 °C.