Spark Logic

AT91SAM7X connection guide

AT91SAM7X TFBGA-100 wiring guide with power, signal assignments, and bench checks.

LQFP-100 100 contacts

TFBGA-100

100 contacts Current package

Microchip Technology · TFBGA-100 · Grid array · Refer to the mechanical drawing for footprint dimensions.

512 KiB flash · 128 KiB SRAM

Power from the on-chip 1.8 V regulator

Required

Use a current-limited 3.3 V supply and the internal regulator. Connect VDDOUT to the core and PLL supplies and decouple every supply pin. Connect all GND contacts to the same ground plane.

4.7 µF + 100 nF at VDDIN and 100 nF per VDDIO and VDDFLASH supply between 3.3 V rail and Ground3.3 V rail4.7 µF + 100 nF at VDDIN and 100 nF per VDDIO and VDDFLASH supplyGround
2.2 µF + 100 nF at VDDOUT and 100 nF per core/PLL supply between 1.8 V rail and Ground1.8 V rail2.2 µF + 100 nF at VDDOUT and 100 nF per core/PLL supplyGround

Bench checks

  • Verify each supply and ground contact against the selected package. Check that the VDDIN rise meets the manufacturer’s minimum 6 V/ms before relying on regulator startup.
  • Verify that VDDOUT settles near 1.8 V. The power-only circuit straps unused dedicated ADC inputs, reference, and USB signals as in the hardware checklist. Leave any USB cable disconnected and disable the unused USB transceiver.
  • Leave XIN, XOUT and PLLRC unused for the internal slow-clock debug fixture. Add the selected clock and loop-filter circuits before switching the firmware to the main clock or PLL.

6260C §3 and 6120K §§5, 7, 24–25

Connection scenarios

Connect the debug serial port

Use a 3.3 V logic-level UART adapter. Cross transmit and receive and share ground. Leave adapter power disconnected from the powered target.

The target TX line goes to adapter RX. The target RX line goes to adapter TX. Both share ground.UART adapterSAM targetRXPA28 · TXTXPA27 · RXGNDGND

Bench checks

  • Enable the debug serial pins and set the UART divider from the actual master clock. Match the terminal’s baud rate and frame settings.
  • Send a known byte and check the actual bit period if the terminal shows corrupted data.

6120K §10.4 and Debug Unit chapter

TFBGA-100 wiring map

Highlighted contacts are used in the required step or selected circuit. Select a contact to inspect it.

12345678910 A B C D E F G H J K
Transparent top view · A1 at the upper left Scroll the map to reach all contacts.
Selected pin details

E7 · VDDIO

Supply · Power

Digital I/O supply. Connect each VDDIO contact and place a local ceramic bypass capacitor nearby.

6120K · Package pinout and signal descriptions

Electrical limits · Pin in the reference

Models and documents

Includes SAM7X128, SAM7X256 and SAM7X512 across the LQFP and TFBGA maps. Select the marked ordering code for the flash size and use the matching silicon errata.

AT91SAM7X512
512 KiB flash · 128 KiB SRAM
AT91SAM7X512-CU
512 KiB flash · 128 KiB SRAM · industrial −40 to +85 °C.
AT91SAM7X512B-CU
512 KiB flash · 128 KiB SRAM · industrial −40 to +85 °C.
AT91SAM7X256
256 KiB flash · 64 KiB SRAM
AT91SAM7X256-CU
256 KiB flash · 64 KiB SRAM · industrial −40 to +85 °C.
AT91SAM7X256B-CU
256 KiB flash · 64 KiB SRAM · industrial −40 to +85 °C.
AT91SAM7X256C-CU
256 KiB flash · 64 KiB SRAM · industrial −40 to +85 °C.
AT91SAM7X128
128 KiB flash · 32 KiB SRAM
AT91SAM7X128-CU
128 KiB flash · 32 KiB SRAM · industrial −40 to +85 °C.
AT91SAM7X128B-CU
128 KiB flash · 32 KiB SRAM · industrial −40 to +85 °C.
AT91SAM7X128C-CU
128 KiB flash · 32 KiB SRAM · industrial −40 to +85 °C.