AT91SAM7X pinout

ARM7TDMI microcontroller family with 128, 256 or 512 KiB flash, USB full-speed device, Ethernet MAC and CAN.

LQFP-100

100 contacts Current package

TFBGA-100 100 contacts

Microchip Technology · LQFP-100 · Quad flat package · Refer to the mechanical drawing for footprint dimensions.

256 KiB flash · 64 KiB SRAM

LQFP-100 pinout

LQFP-100

Top view · Pin 1 at the upper left · Schematic outline Scroll the map to reach all contacts.

Selected pin details

39 · PB12

Bidirectional · GPIO

Programmable input/output line. Peripheral A · ETXER Peripheral B · TCLK0

After reset · PIO input with pull-up at reset. System functions and analog mode can override the digital I/O behavior.

6120K · Package pinout and signal descriptions

Electrical limits · Link to this pin

All 100 pins

Pin	Signal	Direction	Function
1	ADVREF Analog reference	Analog reference	Reference voltage input for the analog converter. Follow the reference limits and connection for the selected use.
2	GND Return	Return	Connect to the ground plane with local return paths for the associated supply capacitors.
3	AD4 Analog input	Analog input	Dedicated analog-to-digital converter input. Keep its voltage between ground and ADVREF.
4	AD5 Analog input	Analog input	Dedicated analog-to-digital converter input. Keep its voltage between ground and ADVREF.
5	AD6 Analog input	Analog input	Dedicated analog-to-digital converter input. Keep its voltage between ground and ADVREF.
6	AD7 Analog input	Analog input	Dedicated analog-to-digital converter input. Keep its voltage between ground and ADVREF.
7	VDDOUT Regulator output	Regulator output	Output of the on-chip 1.8 V regulator. Use the specified output capacitor for regulator stability.
8	VDDIN Supply	Supply	Input to the on-chip regulator. On SAM7X it also supplies the ADC.
9	PB27 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · TIOA2 Peripheral B · PWM0 Extra function · AD0 Package alternate · AD0
10	PB28 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · TIOB2 Peripheral B · PWM1 Extra function · AD1 Package alternate · AD1
11	PB29 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · PCK1 Peripheral B · PWM2 Extra function · AD2 Package alternate · AD2
12	PB30 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · PCK2 Peripheral B · PWM3 Extra function · AD3 Package alternate · AD3
13	PA8 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · RTS1 Peripheral B · SPI0_NPCS2 Package alternate · PGMM0
14	PA9 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · CTS1 Peripheral B · SPI0_NPCS3 Package alternate · PGMM1
15	VDDCORE Supply	Supply	1.8 V supply for the core and embedded logic. Connect all core supply contacts.
16	GND Return	Return	Connect to the ground plane with local return paths for the associated supply capacitors.
17	VDDIO Supply	Supply	Digital I/O supply. Connect each VDDIO contact and place a local ceramic bypass capacitor nearby.
18	PA10 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · TWD Package alternate · PGMM2
19	PA11 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · TWCK Package alternate · PGMM3
20	PA12 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · SPI_NPCS0 Package alternate · PGMD0
21	PA13 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · SPI0_NPCS1 Peripheral B · PCK1 Package alternate · PGMD1
22	PA14 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · SPI0_NPCS2 Peripheral B · IRQ1 Package alternate · PGMD2
23	PA15 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · SPI0_NPCS3 Peripheral B · TCLK2 Package alternate · PGMD3
24	PA16 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · SPI0_MISO Package alternate · PGMD4
25	PA17 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · SPI0_MOSI Package alternate · PGMD5
26	PA18 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · SPI0_SPCK Package alternate · PGMD6
27	PB9 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · EMDIO
28	PB8 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · EMDC
29	PB14 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · ERX3 Peripheral B · SPI0_NPCS2
30	PB13 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · ERX2 Peripheral B · SPI0_NPCS1
31	PB6 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · ERX1
32	GND Return	Return	Connect to the ground plane with local return paths for the associated supply capacitors.
33	VDDIO Supply	Supply	Digital I/O supply. Connect each VDDIO contact and place a local ceramic bypass capacitor nearby.
34	PB5 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · ERX0
35	PB15 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · ERXDV/ECRSDV
36	PB17 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · ERXCK Peripheral B · SPI0_NPCS3
37	VDDCORE Supply	Supply	1.8 V supply for the core and embedded logic. Connect all core supply contacts.
38	PB7 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · ERXER
39	PB12 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · ETXER Peripheral B · TCLK0
40	PB0 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · ETXCK/EREFCK Peripheral B · PCK0
41	PB1 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · ETXEN
42	PB2 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · ETX0
43	PB3 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · ETX1
44	PB10 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · ETX2 Peripheral B · SPI1_NPCS1
45	PB11 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · ETX3 Peripheral B · SPI1_NPCS2
46	PA19 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · CANRX Package alternate · PGMD7
47	PA20 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · CANTX Package alternate · PGMD8
48	VDDIO Supply	Supply	Digital I/O supply. Connect each VDDIO contact and place a local ceramic bypass capacitor nearby.
49	PA21 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · TF Peripheral B · SPI1_NPCS0 Package alternate · PGMD9
50	PA22 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · TK Peripheral B · SPI1_SPCK Package alternate · PGMD10
51	TDI Input	Input	JTAG serial data input. Reference the signal levels to VDDIO.
52	GND Return	Return	Connect to the ground plane with local return paths for the associated supply capacitors.
53	PB16 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · ECOL Peripheral B · SPI1_NPCS3
54	PB4 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · ECRS
55	PA23 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · TD Peripheral B · SPI1_MOSI Package alternate · PGMD11
56	PA24 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · RD Peripheral B · SPI1_MISO Package alternate · PGMD12
57	NRST Bidirectional	Bidirectional	Active-low system reset controlled by the reset controller. Use open-drain drive for external reset.
58	TST Input	Input	Factory test and fast programming selection. Use the documented low strap for normal operation.
59	PA25 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · RK Peripheral B · SPI1_NPCS1 Package alternate · PGMD13
60	PA26 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · RF Peripheral B · SPI1_NPCS2 Package alternate · PGMD14
61	VDDIO Supply	Supply	Digital I/O supply. Connect each VDDIO contact and place a local ceramic bypass capacitor nearby.
62	VDDCORE Supply	Supply	1.8 V supply for the core and embedded logic. Connect all core supply contacts.
63	PB18 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · EF100 Peripheral B · ADTRG
64	PB19 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · PWM0 Peripheral B · TCLK1
65	PB20 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · PWM1 Peripheral B · PCK0
66	PB21 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · PWM2 Peripheral B · PCK1
67	PB22 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · PWM3 Peripheral B · PCK2
68	GND Return	Return	Connect to the ground plane with local return paths for the associated supply capacitors.
69	PB23 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · TIOA0 Peripheral B · DCD1
70	PB24 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · TIOB0 Peripheral B · DSR1
71	PB25 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · TIOA1 Peripheral B · DTR1
72	PB26 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · TIOB1 Peripheral B · RI1
73	PA27 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · DRXD Peripheral B · PCK3 Package alternate · PGMD15
74	PA28 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · DTXD
75	PA29 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · FIQ Peripheral B · SPI1_NPCS3
76	TDO Output	Output	JTAG serial data output. Reference the signal levels to VDDIO.
77	JTAGSEL Input	Input	Selects boundary scan when high. Use the documented low strap for normal debugger access.
78	TMS Input	Input	JTAG test mode select. Reference the signal levels to VDDIO.
79	TCK Input	Input	JTAG test clock. Reference the signal levels to VDDIO.
80	PA30 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · IRQ0 Peripheral B · PCK2
81	PA0 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · RXD0 Package alternate · PGMEN0
82	PA1 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · TXD0 Package alternate · PGMEN1
83	GND Return	Return	Connect to the ground plane with local return paths for the associated supply capacitors.
84	VDDIO Supply	Supply	Digital I/O supply. Connect each VDDIO contact and place a local ceramic bypass capacitor nearby.
85	PA3 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · RTS0 Peripheral B · SPI1_NPCS2
86	PA2 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · SCK0 Peripheral B · SPI1_NPCS1
87	VDDCORE Supply	Supply	1.8 V supply for the core and embedded logic. Connect all core supply contacts.
88	PA4 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · CTS0 Peripheral B · SPI1_NPCS3 Package alternate · PGMNCMD
89	PA5 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · RXD1 Package alternate · PGMRDY
90	PA6 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · TXD1 Package alternate · PGMNOE
91	PA7 Bidirectional	Bidirectional	Programmable input/output line. Peripheral A · SCK1 Peripheral B · SPI0_NPCS1 Package alternate · PGMNVALID
92	ERASE Input	Input	Hardware erase input. Bias low in normal operation and guard against accidental assertion.
93	DDM Bidirectional	Bidirectional	USB device negative data signal. Route with DDP as a differential pair.
94	DDP Bidirectional	Bidirectional	USB device positive data signal. See the hardware checklist for pull-up and routing details.
95	VDDFLASH Supply	Supply	3.3 V nominal supply for the flash charge pump and USB transceiver.
96	GND Return	Return	Connect to the ground plane with local return paths for the associated supply capacitors.
97	XIN Input	Input	Main oscillator amplifier input. Use the recommended crystal or external clock circuit. Package alternate · PGMCK
98	XOUT Output	Output	Main oscillator amplifier output. Use the load network for the chosen crystal.
99	PLLRC Loop filter	Loop filter	PLL loop-filter node. Use the filter values calculated for the chosen operating conditions.
100	VDDPLL Supply	Supply	1.8 V supply for the main oscillator and PLL. Follow the device-specific decoupling and filtering circuit.

Signal assignments

JTAG

Normal ICE/debug access uses JTAGSEL low. Use the target voltage reference on the probe. Clock → TCK · Data in → TDI · Data out → TDO · Mode select → TMS

Debug UART

PIOA peripheral A. Cross TX and RX at the adapter. DRXD → PA27 · DTXD → PA28

USART 0–1

Check the PIO A/B or extra-function selection for each pad. RXD0 → PA0 · TXD0 → PA1 · SCK0 → PA2 · RTS0 → PA3 · CTS0 → PA4 · RXD1 → PA5 · TXD1 → PA6 · SCK1 → PA7 · RTS1 → PA8 · CTS1 → PA9

TWI / I²C

Check the PIO A/B or extra-function selection for each pad. TWD → PA10 · TWCK → PA11

SPI

Check the PIO A/B or extra-function selection for each pad. SPI1_NPCS1 → PA2 · SPI1_NPCS2 → PA3 · SPI1_NPCS3 → PA4 · SPI0_NPCS1 → PA7 · SPI0_NPCS2 → PA8 · SPI0_NPCS3 → PA9 · SPI_NPCS0 → PA12 · SPI0_NPCS1 → PA13 · SPI0_NPCS2 → PA14 · SPI0_NPCS3 → PA15 · SPI0_MISO → PA16 · SPI0_MOSI → PA17 · SPI0_SPCK → PA18 · SPI1_NPCS0 → PA21 · SPI1_SPCK → PA22 · SPI1_MOSI → PA23 · SPI1_MISO → PA24 · SPI1_NPCS1 → PA25 · SPI1_NPCS2 → PA26 · SPI1_NPCS3 → PA29 · SPI1_NPCS1 → PB10 · SPI1_NPCS2 → PB11 · SPI0_NPCS1 → PB13 · SPI0_NPCS2 → PB14 · SPI1_NPCS3 → PB16 · SPI0_NPCS3 → PB17

CAN

Check the PIO A/B or extra-function selection for each pad. CANRX → PA19 · CANTX → PA20

Ethernet MAC

Check the PIO A/B or extra-function selection for each pad. ETXCK/EREFCK → PB0 · ETXEN → PB1 · ETX0 → PB2 · ETX1 → PB3 · ECRS → PB4 · ERX0 → PB5 · ERX1 → PB6 · ERXER → PB7 · EMDC → PB8 · EMDIO → PB9 · ETX2 → PB10 · ETX3 → PB11 · ETXER → PB12 · ERX2 → PB13 · ERX3 → PB14 · ERXDV/ECRSDV → PB15 · ECOL → PB16 · ERXCK → PB17 · EF100 → PB18

PWM

Check the PIO A/B or extra-function selection for each pad. PWM0 → PB19 · PWM1 → PB20 · PWM2 → PB21 · PWM3 → PB22 · PWM0 → PB27 · PWM1 → PB28 · PWM2 → PB29 · PWM3 → PB30

ADC

PB27–PB30 can also operate as digital I/O. AD4–AD7 are dedicated analog inputs. AD0 → PB27 · AD1 → PB28 · AD2 → PB29 · AD3 → PB30 · AD4 → AD4 · AD5 → AD5 · AD6 → AD6 · AD7 → AD7 · Reference → ADVREF

USB device

Use the external pull-up and connection circuit in the hardware checklist. D+ → DDP · D− → DDM

Electrical limits

Parameter	Limit	Conditions and source
Flash and SRAM256 KiB flash · 64 KiB SRAM	256 KiB flash · 64 KiB SRAM	Single-plane flash. 6120K Table 1-1
VDDIN, VDDIO, VDDFLASH3.0–3.6 V	3.0–3.6 V	Nominal 3.3 V for the single-supply configuration. Follow regulator input rise-time requirements. 6120K §5 and 6260C §3
VDDCORE and VDDPLL1.65–1.95 V	1.65–1.95 V	Nominal 1.8 V. The internal regulator can supply both domains with the specified decoupling. 6120K §5 and 6260C §3
Maximum CPU clock55 MHz	55 MHz	Apply the flash wait-state and revision-specific restrictions before setting the clock. 6120K features, Electrical Characteristics and errata

Models and documents

Includes SAM7X128, SAM7X256 and SAM7X512 across the LQFP and TFBGA maps. Select the marked ordering code for the flash size and use the matching silicon errata.

AT91SAM7X512: 512 KiB flash · 128 KiB SRAM
AT91SAM7X512-AU: 512 KiB flash · 128 KiB SRAM · industrial −40 to +85 °C.
AT91SAM7X512B-AU: 512 KiB flash · 128 KiB SRAM · industrial −40 to +85 °C.
AT91SAM7X512B-AUR: 512 KiB flash · 128 KiB SRAM · industrial −40 to +85 °C · tape and reel.
AT91SAM7X256: 256 KiB flash · 64 KiB SRAM
AT91SAM7X256-AU: 256 KiB flash · 64 KiB SRAM · industrial −40 to +85 °C.
AT91SAM7X256B-AU: 256 KiB flash · 64 KiB SRAM · industrial −40 to +85 °C.
AT91SAM7X256C-AU: 256 KiB flash · 64 KiB SRAM · industrial −40 to +85 °C.
AT91SAM7X128: 128 KiB flash · 32 KiB SRAM
AT91SAM7X128-AU: 128 KiB flash · 32 KiB SRAM · industrial −40 to +85 °C.
AT91SAM7X128B-AU: 128 KiB flash · 32 KiB SRAM · industrial −40 to +85 °C.
AT91SAM7X128C-AU: 128 KiB flash · 32 KiB SRAM · industrial −40 to +85 °C.

SAM7X512 / SAM7X256 / SAM7X128 data sheet· 6120K · Package tables §4, PIO multiplexing §§10.4–10.5, ordering §40 and errata §41.
SAM7X and SAM7XC schematic checklist· 6260C · Regulator, reset, JTAG, external clock and I/O wiring.
SAM source register· Manufacturer source identifiers, retrieval dates, applicability and SHA-256 digests.