Spark Logic

ATmega16U2 connection guide

ATmega16U2 QFN-32 wiring guide with power, signal assignments, and bench checks.

TQFP-32 32 contacts

QFN-32

33 contacts Current package

Microchip Technology · 32 numbered contacts. The underside pad appears below the contact map. See the individual package drawings for footprint dimensions.

16 KiB flash · 512 B SRAM · 512 B EEPROM. Choose the marked order code for voltage, clock, and temperature.

Power and reset

Required

Use a current-limited supply at a voltage permitted by the order code and system clock. Tie the listed supply pins to that rail. Fit one 100 nF ceramic capacitor close to each supply-and-ground pair. Use a 10 kΩ reset pull-up for this bench circuit.

100 nF per supply pair between Target rail and GroundTarget rail100 nF per supply pairGround
10 kΩ between Target rail and ResetTarget rail10 kΩReset
1 µF between USB regulator output and GroundUSB regulator output1 µFGround

Bench checks

  • With power off, check for a short across the supply. Power on and measure voltage at every supply pin and at reset.
  • The factory configuration uses the internal 8 MHz RC oscillator divided down to 1 MHz. Check CKSEL on a used device.
  • Keep the USB cable disconnected for this fixture. For USB operation, follow the data sheet’s bus-powered or self-powered circuit.

AN2519 §§2–3 and 7799E · Pin descriptions and clock source

Connection scenarios

Connect USART1 to a logic-level serial adapter

Use a UART adapter that supports the target’s I/O voltage. Cross the transmit and receive lines. Leave adapter power disconnected when using the bench supply.

USART1 TX connects to adapter RX. USART1 RX connects to adapter TX. Both share ground.UART adapterAVR targetRXPD3 · TXDTXPD2 · RXDGNDGND

Bench checks

  • Configure both sides for the same baud rate, frame length, parity and stop bits. Base the MCU baud divider on the actual clock after prescaling.
  • Send a known byte such as 0x55 from the MCU and check that it arrives unchanged. If it fails, inspect TX idle voltage and bit period before attaching the adapter TX line.

7799E · USART1 asynchronous operation and pin assignments

QFN-32 wiring map

Highlighted contacts are used in the required step or selected circuit. Select a contact to inspect it.

Top view · Pin 1 at the upper left · Schematic outline
EP is the exposed center pad on the underside.
Selected pin details

24 · PC1

Input / I/O · Reset / preset

Active-low reset input by default. Use as GPIO only where the reset-disable fuse is supported and configured.

7799E · Pinout and peripheral signal descriptions

Electrical limits · Pin in the reference

Models and documents

Each package lists the documented order codes and variants covered by this map. Select the marked model to see its peripheral assignments and memory. Check the exact order code and datasheet revision before laying out a PCB.

ATmega16U2
16 KiB flash · 512 B SRAM · 512 B EEPROM. Choose the marked order code for voltage, clock, and temperature.
ATmega16U2-MU
16 KiB flash · 512 B SRAM · 512 B EEPROM · 2.7–5.5 V · 16 MHz maximum · -40 to +85 °C