Spark Logic

ATmega32U4 connection guide

ATmega32U4 QFN-44 wiring guide with power, signal assignments, and bench checks.

TQFP-44 44 contacts

QFN-44

45 contacts Current package

Microchip Technology · 44 numbered contacts. The underside pad appears below the contact map. See the individual package drawings for footprint dimensions.

32 KiB flash · 2.5 KiB SRAM · 1 KiB EEPROM · 2.7–5.5 V · 16 MHz maximum · -40 to +85 °C

Power and reset

Required

Use a current-limited supply at a voltage permitted by the order code and system clock. Tie the listed supply pins to that rail. Fit one 100 nF ceramic capacitor close to each supply-and-ground pair. Use a 10 kΩ reset pull-up for this bench circuit.

100 nF per supply pair between Target rail and GroundTarget rail100 nF per supply pairGround
10 kΩ between Target rail and ResetTarget rail10 kΩReset
1 µF between USB regulator output and GroundUSB regulator output1 µFGround

Bench checks

  • With power off, check for a short across the supply. Power on and measure voltage at every supply pin and at reset.
  • The standard device ships with external crystal selected. The RC-suffix device ships with its internal oscillator selected. Check CKSEL on a used device.
  • Keep the USB cable disconnected for this fixture. For USB operation, follow the data sheet’s bus-powered or self-powered circuit.

AN2519 §§2–3 and 7766J · Pin descriptions and clock source

Connection scenarios

Program and read the signature over ISP

Start from the power and reset circuit. Attach a voltage-compatible AVR in-system programmer and use the target voltage as its reference. Connect reset, serial data in/out, and SCK as shown.

AVR programmer wired to target voltage reference, ground, reset, serial data in/out and clock.ProgrammerAVR targetVTGVCCGNDGNDRESETRESETMOSIPB2MISOPB3SCKPB1

Bench checks

  • Read the device signature before writing flash or fuses. If it fails, verify target power, the clock source, programmer direction, and the selected device.
  • If the programmer offers an adjustable SCK, start below one quarter of the target clock and check the data sheet’s SCK high and low timing. Disconnect or isolate other peripherals that drive the programming lines.
  • Disable power output on the programmer if the target has its own bench supply. Confirm the programmer’s VTG behavior in its manual.

AN2519 §4.1 and 7766J · Serial Programming Pin Mapping

QFN-44 wiring map

Highlighted contacts are used in the required step or selected circuit. Select a contact to inspect it.

Top view · Pin 1 at the upper left · Schematic outline
EP is the exposed center pad on the underside.
Selected pin details

37 · PF6

Bidirectional · GPIO

General-purpose digital I/O. Alternate assignments: TDO (JTAG), ADC6 (ADC).

After reset · GPIO driver is high impedance during reset. Clock, debug, and alternate-function use depend on fuse and peripheral configuration.

7766J · Pinout and peripheral signal descriptions

Electrical limits · Pin in the reference

Models and documents

Each package lists the documented order codes and variants covered by this map. Select the marked model to see its peripheral assignments and memory. Check the exact order code and datasheet revision before laying out a PCB.

ATmega32U4
32 KiB flash · 2.5 KiB SRAM · 1 KiB EEPROM. Choose the marked order code for voltage, clock, and temperature.
ATmega32U4-MU
32 KiB flash · 2.5 KiB SRAM · 1 KiB EEPROM · 2.7–5.5 V · 16 MHz maximum · -40 to +85 °C
ATmega32U4RC-MU
32 KiB flash · 2.5 KiB SRAM · 1 KiB EEPROM · 2.7–5.5 V · 16 MHz maximum · -40 to +85 °C