Spark Logic

ATSAM3X8E connection guide

ATSAM3X8E LFBGA-144 wiring guide with power, signal assignments, and bench checks.

LQFP-144 144 contacts

LFBGA-144

144 contacts Current package

Microchip Technology · LFBGA-144 · Grid array · Refer to the mechanical drawing for footprint dimensions.

512 KiB flash in two 256 KiB banks. SRAM: 64 KiB + 32 KiB system banks and 4 KiB NAND controller SRAM.

Power from the on-chip 1.8 V regulator

Required

Use a current-limited 3.3 V supply with the internal regulator enabled. Fit the 10 µH series inductors and the damped branches as in AT03462 §2.1.1. The 1 Ω resistor and 4.7 µF capacitor on each filtered rail are in series to ground.

10 µF minimum at VDDIN, 4.7 µF main branch and local 100 nF bypasses between 3.3 V rail and Ground3.3 V rail10 µF minimum at VDDIN, 4.7 µF main branch and local 100 nF bypassesGround
4.7 µF minimum at VDDOUT and 100 nF per VDDCORE contact between 1.8 V core rail and Ground1.8 V core rail4.7 µF minimum at VDDOUT and 100 nF per VDDCORE contactGround
1 kΩ between Erase strap and GroundErase strap1 kΩGround
6.8 kΩ ±1% between USB bias reference and GroundUSB bias reference6.8 kΩ ±1%Ground
10 pF between USB bias reference and GroundUSB bias reference10 pFGround
100 nF before the USB PHY inductor between 3.3 V rail and Ground3.3 V rail100 nF before the USB PHY inductorGround
100 nF after the inductor between USB PHY filtered rail and GroundUSB PHY filtered rail100 nF after the inductorGround
1 Ω between USB PHY filtered rail and USB PHY damping nodeUSB PHY filtered rail1 ΩUSB PHY damping node
4.7 µF between USB PHY damping node and GroundUSB PHY damping node4.7 µFGround
100 nF before the Analog inductor between 3.3 V rail and Ground3.3 V rail100 nF before the Analog inductorGround
100 nF after the inductor between Analog filtered rail and GroundAnalog filtered rail100 nF after the inductorGround
1 Ω between Analog filtered rail and Analog damping nodeAnalog filtered rail1 ΩAnalog damping node
4.7 µF between Analog damping node and GroundAnalog damping node4.7 µFGround
100 nF before the PLL inductor between 1.8 V core rail and Ground1.8 V core rail100 nF before the PLL inductorGround
100 nF after the inductor between PLL filtered rail and GroundPLL filtered rail100 nF after the inductorGround
1 Ω between PLL filtered rail and PLL damping nodePLL filtered rail1 ΩPLL damping node
4.7 µF between PLL damping node and GroundPLL damping node4.7 µFGround

Bench checks

  • Verify each ground and supply contact against the selected package. Confirm all 3.3 V domains and the 1.8 V core and PLL domains before connecting the debugger.
  • This fixture keeps USB and the ADC disabled. Ground ADVREF and keep ERASE/PC0 low. Leave NRST and NRSTB available for reset inputs as needed.
  • For a working analog reference, backup-mode entry, or USB data, follow the dedicated checklist section and fit its external circuit before enabling that peripheral.

AT03462 §§2.1.1, 2.3–2.5, 2.8–2.9 and 11057C §5

Connection scenarios

Connect a Serial Wire Debug probe

Start with the 3.3 V fixture. Use a probe with 3.3 V target signaling and connect its voltage reference and return. Fit the clock and data pull-ups from the hardware checklist.

100 kΩ between Target I/O voltage and Debug clockTarget I/O voltage100 kΩDebug clock
100 kΩ between Target I/O voltage and Debug dataTarget I/O voltage100 kΩDebug data

Bench checks

  • Set the probe to SWD with a conservative initial clock. Check target voltage, JTAGSEL low and correct wire order if it cannot read the debug ID.
  • For optional trace connect SWO to PB30. Check probe connector pin numbers against its own documentation.

AT03462 §§2.3–2.4 and 11057C §6

LFBGA-144 wiring map

Highlighted contacts are used in the required step or selected circuit. Select a contact to inspect it.

123456789101112 A B C D E F G H J K L M
Transparent top view · A1 at the upper left Scroll the map to reach all contacts.
Selected pin details

A2 · PB23

Bidirectional · GPIO

Programmable input/output line. Peripheral A · CTS2 Peripheral B · SPI0_NPCS3 Extra function · WKUP14

After reset · PIO input with pull-up at reset. System functions and analog mode can override the digital I/O behavior.

11057C · Package pinout and signal descriptions

Electrical limits · Pin in the reference

Models and documents

Includes the 144-lead LQFP and 144-ball LFBGA order codes in 11057C §48. The package power pins differ. GPIO peripheral choices use the SAM3X rows in the PIO tables.

ATSAM3X8E
512 KiB flash in two 256 KiB banks. SRAM: 64 KiB + 32 KiB system banks and 4 KiB NAND controller SRAM.
ATSAM3X8EA-CU
MRL A · 84 MHz Cortex-M3 · industrial temperature −40 to +85 °C.