Spark Logic

ATtiny45 / ATtiny85 connection guide

ATtiny45 / ATtiny85 (TSSOP-8) connection guide. Power and reset. Program and read the signature over ISP.

PackageContactsDetails
PDIP-8 8 8 numbered contacts. See the individual package drawings for footprint dimensions.
SOIC-8 8 8 numbered contacts. See the individual package drawings for footprint dimensions.
TSSOP-8 8 8 numbered contacts. See the individual package drawings for footprint dimensions.
QFN/MLF-20 21 20 numbered contacts. The underside pad appears below the contact map. See the individual package drawings for footprint dimensions.

Microchip Technology

Device variants · TSSOP-8

DeviceFlashSRAMEEPROMSupplyMax clockTemperature
ATtiny45 4 KiB 256 B 256 B — — —
ATtiny45V-10XU 4 KiB 256 B 256 B 1.8–5.5 V 10 MHz -40 to +85 °C
ATtiny45V-10XUR 4 KiB 256 B 256 B 1.8–5.5 V 10 MHz -40 to +85 °C
ATtiny45-20XU 4 KiB 256 B 256 B 2.7–5.5 V 20 MHz -40 to +85 °C
ATtiny45-20XUR 4 KiB 256 B 256 B 2.7–5.5 V 20 MHz -40 to +85 °C

Power and reset

Required

Use a current-limited supply at a voltage permitted by the order code and system clock. Tie the listed supply pins to that rail. Fit one 100 nF ceramic capacitor close to each supply-and-ground pair. Use a 10 kΩ reset pull-up for this bench circuit.

  • Target rail
    • Bench supply positive
  • Ground
    • Bench supply return
  • Reset
100 nF per supply pair between Target rail and GroundTarget rail100 nF per supply pairGround
10 kΩ between Target rail and ResetTarget rail10 kΩReset

Bench checks

  • RESET is active by default. GPIO use requires disabling RESET via RSTDISBL and keeping debugWIRE inactive. For ADC0, check the reset threshold and internal pull-up while RESET is enabled. Active debugWIRE also uses this pad.
  • Give unused GPIO inputs a defined level. Enable the internal pull-up or use an external pull-up or pull-down if a defined level is needed during reset. Avoid a direct rail connection that could short an accidental output.
  • With power off, check for a short across the supply. Power on and measure voltage at every supply pin and at reset.
  • Check the clock source configured by CKSEL. If a used part expects an external clock, provide it before attempting serial programming.

AN2519 §§2–3 and 2586Q · Pin descriptions and clock source

Connection scenarios

USI two-wire (I²C)

Connect the matching SDA and SCL lines and share ground. Size the pull-ups for the bus speed and capacitance, accounting for any already fitted on the bus.

  • SDA
    • ↔
    • Peripheral SDA
  • SCL
    • ↔
    • Peripheral SCL
  • Ground
    • Peripheral GND
  • Pull-up rail
    • Compatible bus supply
SDA pull-up between Pull-up rail and SDAPull-up railSDA pull-upSDA
SCL pull-up between Pull-up rail and SCLPull-up railSCL pull-upSCL

Bench checks

  • Fit a separate external pull-up on SDA (PB0) and SCL (PB2) to the compatible bus supply. USI disables both internal pull-ups in this mode.
  • Check that SDA and SCL both idle high at the bus voltage.

2586Q · §§15.3.4 and 15.4.2

TSSOP-8 wiring map

External wiring example · USI two-wire (I²C)

Highlighted contacts are used in the required step or selected circuit. Select a contact to highlight its wiring nets.

TSSOP-8 · Marking side · Pin 1 at the upper left
Selected pin details

1 · PB5

Input / I/O · Reset / preset

Active-low reset input by default. Use as GPIO only where the reset-disable fuse is supported and configured. Alternate assignments: ADC0 (ADC), PCINT5 (EXINT).

Wiring requirements

  • RESET, GPIO or ADC0 on PB5. RESET is active by default. GPIO use requires disabling RESET via RSTDISBL and keeping debugWIRE inactive. For ADC0, check the reset threshold and internal pull-up while RESET is enabled. Active debugWIRE also uses this pad.

    2586Q · §10.3.1 and Table 10-4, pp. 60–63

  • Unused GPIO. Give unused GPIO inputs a defined level. Enable the internal pull-up or use an external pull-up or pull-down if a defined level is needed during reset. Avoid a direct rail connection that could short an accidental output.

    2586Q · §10.2.6, p. 57

2586Q · Pinout and peripheral signal descriptions

Connected nets

Electrical limits · Pin in the reference

Manufacturer documents

Each package lists the documented order codes and variants covered by this map. Select the marked model to see its peripheral assignments and memory. Check the exact order code and datasheet revision before laying out a PCB.