Spark Logic

CS43L22 stereo audio DAC connection guide

CS43L22 stereo audio DAC QFN-40 wiring guide with power, signal assignments, and bench checks.

QFN-40

41 contacts Current package

Cirrus Logic · 40-contact QFN with ground/thermal pad.

Power the core while holding reset

Required

Use a regulated 2.5 V rail for VA, VD, VP and +VHP, and 3.3 V for VL. Keep RESET low while both rails settle. Place decoupling at the individual pins and leave the speaker and headphone outputs unloaded.

CVD1 1 µF between 2.5 V supply and Ground2.5 V supplyCVD1 1 µFGround
CVD2 100 nF between 2.5 V supply and Ground2.5 V supplyCVD2 100 nFGround
CVA 100 nF between 2.5 V supply and Ground2.5 V supplyCVA 100 nFGround
CVHP1 1 µF between 2.5 V supply and Ground2.5 V supplyCVHP1 1 µFGround
CVHP2 100 nF between 2.5 V supply and Ground2.5 V supplyCVHP2 100 nFGround
CVP1 100 nF between 2.5 V supply and Ground2.5 V supplyCVP1 100 nFGround
CVP2 100 nF between 2.5 V supply and Ground2.5 V supplyCVP2 100 nFGround
CVP3 10 µF between 2.5 V supply and Ground2.5 V supplyCVP3 10 µFGround
CVL 100 nF between 3.3 V interface supply and Ground3.3 V interface supplyCVL 100 nFGround
CFILT 10 µF between Reference filter and GroundReference filterCFILT 10 µFGround
CVQ 1 µF between Quiescent filter and GroundQuiescent filterCVQ 1 µFGround
CFA 150 pF C0G between Analog filter A and GroundAnalog filter ACFA 150 pF C0GGround
CFB 150 pF C0G between Analog filter B and GroundAnalog filter BCFB 150 pF C0GGround
CFLY 1 µF X7R between Pump positive and Pump negativePump positiveCFLY 1 µF X7RPump negative
CHP 1 µF X7R between Negative headphone rail and GroundNegative headphone railCHP 1 µF X7RGround

Bench checks

  • Check both supply voltages at the package before releasing RESET. Verify the exposed pad and both ground pins have a low-impedance path to board ground.

Cirrus Logic DS792F2, Figure 1 and § 4.9. Component values follow the typical circuit.

Connection scenarios

Read the DAC identity over I²C

Wire SCL and SDA to the 3.3 V controller with 2 kΩ pull-ups to VL. Release RESET after the rails settle. Keep the internal power-down setting in register 0x02.

CVD1 1 µF between 2.5 V supply and Ground2.5 V supplyCVD1 1 µFGround
CVD2 100 nF between 2.5 V supply and Ground2.5 V supplyCVD2 100 nFGround
CVA 100 nF between 2.5 V supply and Ground2.5 V supplyCVA 100 nFGround
CVHP1 1 µF between 2.5 V supply and Ground2.5 V supplyCVHP1 1 µFGround
CVHP2 100 nF between 2.5 V supply and Ground2.5 V supplyCVHP2 100 nFGround
CVP1 100 nF between 2.5 V supply and Ground2.5 V supplyCVP1 100 nFGround
CVP2 100 nF between 2.5 V supply and Ground2.5 V supplyCVP2 100 nFGround
CVP3 10 µF between 2.5 V supply and Ground2.5 V supplyCVP3 10 µFGround
CVL 100 nF between 3.3 V interface supply and Ground3.3 V interface supplyCVL 100 nFGround
CFILT 10 µF between Reference filter and GroundReference filterCFILT 10 µFGround
CVQ 1 µF between Quiescent filter and GroundQuiescent filterCVQ 1 µFGround
CFA 150 pF C0G between Analog filter A and GroundAnalog filter ACFA 150 pF C0GGround
CFB 150 pF C0G between Analog filter B and GroundAnalog filter BCFB 150 pF C0GGround
CFLY 1 µF X7R between Pump positive and Pump negativePump positiveCFLY 1 µF X7RPump negative
CHP 1 µF X7R between Negative headphone rail and GroundNegative headphone railCHP 1 µF X7RGround
RSCL 2 kΩ between 3.3 V interface supply and I²C clock3.3 V interface supplyRSCL 2 kΩI²C clock
RSDA 2 kΩ between 3.3 V interface supply and I²C data3.3 V interface supplyRSDA 2 kΩI²C data

Bench checks

  • At seven-bit address 0x4A, set the register pointer to 0x01, then read one byte.
  • For a CS43L22, the result masked with 0xF8 equals 0xE0. The low three bits report the silicon revision.

Cirrus Logic DS792F2, §§ 4.9, 4.12 and 7.1.

QFN-40 wiring map

Highlighted contacts are used in the required step or selected circuit. Select a contact to inspect it.

Locate the pin 1 mark and use the top view unless the drawing specifies a different view.
EP is the exposed center pad on the underside.
Selected pin details

14 · HP/LINE_OUTB

Output · Outputs

Channel B headphone or line-level output.

Cirrus Logic DS792F2, § 1

Electrical limits · Pin in the reference

Models and documents

The map covers the bare 40-contact QFN. The control-port fixture keeps the audio paths powered down and confirms identity before loading an audio configuration.

CS43L22-CNZ
Rail packing.
CS43L22-CNZR
Tape and reel.
  • Cirrus Logic DS792F2· Pin descriptions, Figure 1, power sequencing, I²C and identification register.
  • Source register· Document revisions, applicable order codes, consulted sections and available file checksums.