Spark Logic

CY7C68013A EZ-USB FX2LP controller connection guide

CY7C68013A EZ-USB FX2LP controller QFN-56 wiring guide with power, signal assignments, and bench checks.

SSOP-56 56 contacts

QFN-56

57 contacts Current package

Infineon / Cypress · 8 × 8 mm sawn QFN, 24 GPIOs and 16 KiB RAM.

Bring up the clock and reset

Required

Use a 3.3 V source with a controlled ramp to operating voltage of at least 200 µs. Hold RESET# low for at least 5 ms after the supply is stable. Use a 24 MHz fundamental parallel-resonant crystal with ±100 ppm frequency tolerance and the recommended load.

C3 100 nF X7R at pin 3 between 3.3 V and Ground3.3 VC3 100 nF X7R at pin 3Ground
C7 10 nF at pin 7 between 3.3 V and Ground3.3 VC7 10 nF at pin 7Ground
C11 1 nF C0G at pin 11 between 3.3 V and Ground3.3 VC11 1 nF C0G at pin 11Ground
C17 100 nF X7R at pin 17 between 3.3 V and Ground3.3 VC17 100 nF X7R at pin 17Ground
C27 100 nF X7R at pin 27 between 3.3 V and Ground3.3 VC27 100 nF X7R at pin 27Ground
C32 100 nF X7R at pin 32 between 3.3 V and Ground3.3 VC32 100 nF X7R at pin 32Ground
C43 100 nF X7R at pin 43 between 3.3 V and Ground3.3 VC43 100 nF X7R at pin 43Ground
C55 100 nF X7R at pin 55 between 3.3 V and Ground3.3 VC55 100 nF X7R at pin 55Ground
RSCL 4.7 kΩ between 3.3 V and Boot clock3.3 VRSCL 4.7 kΩBoot clock
RSDA 4.7 kΩ between 3.3 V and Boot data3.3 VRSDA 4.7 kΩBoot data
Y1 24 MHz parallel resonance between Crystal input and Crystal outputCrystal inputY1 24 MHz parallel resonanceCrystal output
CX1 12 pF C0G between Crystal input and GroundCrystal inputCX1 12 pF C0GGround
CX2 12 pF C0G between Crystal output and GroundCrystal outputCX2 12 pF C0GGround

Bench checks

  • Check 3.3 V at every supply lead, WAKEUP high, and RESERVED at ground before releasing reset.
  • Probe CLKOUT with a high-impedance scope. Expect a 12 MHz clock with the default CPU setting.

Infineon / Cypress 38-08032 Rev. AD, Figure 1, Table 11 and operating conditions; Infineon / Cypress AN15456 Rev. G, § 3. The crystal capacitors assume the layout in Figure 1.

Connection scenarios

Check USB boot without an EEPROM

On a USB-ready PCB, route D+ and D− as a 90 Ω differential pair to the USB device connector. Use the bus-powered regulator and reset architecture in AN15456 Figure 9. Feed 3.3 V from that regulator for this test and omit the boot EEPROM.

C3 100 nF X7R at pin 3 between 3.3 V and Ground3.3 VC3 100 nF X7R at pin 3Ground
C7 10 nF at pin 7 between 3.3 V and Ground3.3 VC7 10 nF at pin 7Ground
C11 1 nF C0G at pin 11 between 3.3 V and Ground3.3 VC11 1 nF C0G at pin 11Ground
C17 100 nF X7R at pin 17 between 3.3 V and Ground3.3 VC17 100 nF X7R at pin 17Ground
C27 100 nF X7R at pin 27 between 3.3 V and Ground3.3 VC27 100 nF X7R at pin 27Ground
C32 100 nF X7R at pin 32 between 3.3 V and Ground3.3 VC32 100 nF X7R at pin 32Ground
C43 100 nF X7R at pin 43 between 3.3 V and Ground3.3 VC43 100 nF X7R at pin 43Ground
C55 100 nF X7R at pin 55 between 3.3 V and Ground3.3 VC55 100 nF X7R at pin 55Ground
RSCL 4.7 kΩ between 3.3 V and Boot clock3.3 VRSCL 4.7 kΩBoot clock
RSDA 4.7 kΩ between 3.3 V and Boot data3.3 VRSDA 4.7 kΩBoot data
Y1 24 MHz parallel resonance between Crystal input and Crystal outputCrystal inputY1 24 MHz parallel resonanceCrystal output
CX1 12 pF C0G between Crystal input and GroundCrystal inputCX1 12 pF C0GGround
CX2 12 pF C0G between Crystal output and GroundCrystal outputCX2 12 pF C0GGround

Bench checks

  • Verify the controller supply remains within 3.0–3.6 V during enumeration. Keep 5 V VBUS on the regulator input side.
  • With RESET# released and SCL and SDA pulled high, the host should enumerate VID 04B4 and PID 8613 if no EEPROM responds.
  • If it fails, inspect the differential pair and the reset interval before loading firmware.

Infineon / Cypress 38-08032 Rev. AD, USB Boot Methods; Infineon / Cypress AN15456 Rev. G, USB routing and reset.

QFN-56 wiring map

Highlighted contacts are used in the required step or selected circuit. Select a contact to inspect it.

Locate the pin 1 mark and use the top view unless the drawing specifies a different view.
EP is the exposed center pad on the underside.
Selected pin details

44 · WAKEUP

Input · Inputs

Suspend wake input. Defaults to active low; keep high when unused.

Infineon / Cypress 38-08032 Rev. AD, Figure 10 and Table 11

Electrical limits · Pin in the reference

Models and documents

The interactive maps cover 56-pin SSOP and QFN. The 56-ball VFBGA, 100-pin TQFP and 128-pin TQFP use separate pin assignments in Figures 7–8 and 11 of the manufacturer data sheet.

CY7C68013A-56LTXC
Commercial sawn QFN.
CY7C68013A-56LTXCT
Commercial sawn QFN tape and reel.
CY7C68013A-56LTXI
Industrial sawn QFN.