CY7C68013A EZ-USB FX2LP controller pinout

A high-speed USB 2.0 device controller with an enhanced 8051 core, 16 KiB internal RAM and a configurable parallel FIFO interface.

SSOP-56 56 contacts

QFN-56

57 contacts Current package

Infineon / Cypress · 8 × 8 mm sawn QFN, 24 GPIOs and 16 KiB RAM.

Commercial sawn QFN tape and reel.

QFN-56 pinout

Locate the pin 1 mark and use the top view unless the drawing specifies a different view.
EP is the exposed center pad on the underside.

Selected pin details

45 · PD0/FD8

Bidirectional · GPIO

Port D bit 0 or FIFO data bit 8, selected by interface mode.

Infineon / Cypress 38-08032 Rev. AD, Figure 10 and Table 11

Electrical limits · Link to this pin

All 57 pins

Pin	Signal	Direction	Function
1	RDY0/SLRD Input	Input	GPIF ready input 0 or slave FIFO read strobe.
2	RDY1/SLWR Input	Input	GPIF ready input 1 or slave FIFO write strobe.
3	AVCC Supply	Supply	Analog 3.3 V supply for the USB circuitry.
4	XTALOUT Output	Output	Crystal oscillator output. Leave open when using an external CMOS clock.
5	XTALIN Input	Input	24 MHz crystal or 3.3 V external clock input.
6	AGND Return	Return	Analog ground. Use a short path to the ground plane.
7	AVCC Supply	Supply	Analog 3.3 V supply for the USB circuitry.
8	DPLUS Bidirectional	Bidirectional	USB D+ signal. Route with D− as a controlled-impedance differential pair.
9	DMINUS Bidirectional	Bidirectional	USB D− signal. Route with D+ as a controlled-impedance differential pair.
10	AGND Return	Return	Analog ground. Use a short path to the ground plane.
11	VCC Supply	Supply	Digital 3.3 V supply. Bypass at the package lead.
12	GND Return	Return	Digital ground. Connect to a continuous ground plane.
13	IFCLK Bidirectional	Bidirectional	FIFO / GPIF interface clock. May use the internal or an external source.
14	RESERVED Reserved input	Reserved input	Reserved pin. Connect directly to ground.
15	SCL Bidirectional	Bidirectional	Boot I²C clock. Pull up to 3.3 V even with no EEPROM installed.
16	SDA Bidirectional	Bidirectional	Boot I²C data. Pull up to 3.3 V even with no EEPROM installed.
17	VCC Supply	Supply	Digital 3.3 V supply. Bypass at the package lead.
18	PB0/FD0 Bidirectional	Bidirectional	Port B bit 0 or FIFO data bit 0, selected by interface mode.
19	PB1/FD1 Bidirectional	Bidirectional	Port B bit 1 or FIFO data bit 1, selected by interface mode.
20	PB2/FD2 Bidirectional	Bidirectional	Port B bit 2 or FIFO data bit 2, selected by interface mode.
21	PB3/FD3 Bidirectional	Bidirectional	Port B bit 3 or FIFO data bit 3, selected by interface mode.
22	PB4/FD4 Bidirectional	Bidirectional	Port B bit 4 or FIFO data bit 4, selected by interface mode.
23	PB5/FD5 Bidirectional	Bidirectional	Port B bit 5 or FIFO data bit 5, selected by interface mode.
24	PB6/FD6 Bidirectional	Bidirectional	Port B bit 6 or FIFO data bit 6, selected by interface mode.
25	PB7/FD7 Bidirectional	Bidirectional	Port B bit 7 or FIFO data bit 7, selected by interface mode.
26	GND Return	Return	Digital ground. Connect to a continuous ground plane.
27	VCC Supply	Supply	Digital 3.3 V supply. Bypass at the package lead.
28	GND Return	Return	Digital ground. Connect to a continuous ground plane.
29	CTL0/FLAGA Output	Output	GPIF control output 0 or slave FIFO flag A.
30	CTL1/FLAGB Output	Output	GPIF control output 1 or slave FIFO flag B.
31	CTL2/FLAGC Output	Output	GPIF control output 2 or slave FIFO flag C.
32	VCC Supply	Supply	Digital 3.3 V supply. Bypass at the package lead.
33	PA0/INT0# Bidirectional	Bidirectional	Port A bit 0 or external interrupt 0.
34	PA1/INT1# Bidirectional	Bidirectional	Port A bit 1 or external interrupt 1.
35	PA2/SLOE Bidirectional	Bidirectional	Port A bit 2 or slave FIFO output enable.
36	PA3/WU2 Bidirectional	Bidirectional	Port A bit 3 or alternate wake input.
37	PA4/FIFOADR0 Bidirectional	Bidirectional	Port A bit 4 or FIFO endpoint select address bit 0.
38	PA5/FIFOADR1 Bidirectional	Bidirectional	Port A bit 5 or FIFO endpoint select address bit 1.
39	PA6/PKTEND Bidirectional	Bidirectional	Port A bit 6 or slave FIFO packet-end input.
40	PA7/FLAGD/SLCS# Bidirectional	Bidirectional	Port A bit 7, slave FIFO flag D or slave chip select.
41	GND Return	Return	Digital ground. Connect to a continuous ground plane.
42	RESET# Input	Input	Active-low hardware reset. Keep asserted while the supply and reference clock settle.
43	VCC Supply	Supply	Digital 3.3 V supply. Bypass at the package lead.
44	WAKEUP Input	Input	Suspend wake input. Defaults to active low; keep high when unused.
45	PD0/FD8 Bidirectional	Bidirectional	Port D bit 0 or FIFO data bit 8, selected by interface mode.
46	PD1/FD9 Bidirectional	Bidirectional	Port D bit 1 or FIFO data bit 9, selected by interface mode.
47	PD2/FD10 Bidirectional	Bidirectional	Port D bit 2 or FIFO data bit 10, selected by interface mode.
48	PD3/FD11 Bidirectional	Bidirectional	Port D bit 3 or FIFO data bit 11, selected by interface mode.
49	PD4/FD12 Bidirectional	Bidirectional	Port D bit 4 or FIFO data bit 12, selected by interface mode.
50	PD5/FD13 Bidirectional	Bidirectional	Port D bit 5 or FIFO data bit 13, selected by interface mode.
51	PD6/FD14 Bidirectional	Bidirectional	Port D bit 6 or FIFO data bit 14, selected by interface mode.
52	PD7/FD15 Bidirectional	Bidirectional	Port D bit 7 or FIFO data bit 15, selected by interface mode.
53	GND Return	Return	Digital ground. Connect to a continuous ground plane.
54	CLKOUT Output	Output	Clock output. Defaults to 12 MHz after startup and is programmable.
55	VCC Supply	Supply	Digital 3.3 V supply. Bypass at the package lead.
56	GND Return	Return	Digital ground. Connect to a continuous ground plane.
PAD	EP Thermal pad	Thermal pad	Solder the die paddle to the PCB thermal pad connected to the ground plane.

Signal assignments

USB device data

The two USB data pins attach to the controlled-impedance differential pair.

I²C boot interface

A supported boot EEPROM can supply descriptors or firmware. Use pull-ups even when booting without one.

16-bit slave FIFO data and controls

Firmware selects the slave FIFO mode and controls polarity and endpoint configuration.

Electrical limits

Parameter	Limit	Conditions and source
Supply3.00–3.60 V	3.00–3.60 V	VCC and AVCC. Observe the rise-time and reset requirements. Infineon / Cypress 38-08032 Rev. AD, operating conditions
Crystal reference24 MHz ±100 ppm	24 MHz ±100 ppm	Fundamental parallel resonance. Check load and drive level in the oscillator section. Infineon / Cypress 38-08032 Rev. AD, Figure 1
USB signaling12 or 480 Mbit/s	12 or 480 Mbit/s	Full speed or high speed. Infineon / Cypress 38-08032 Rev. AD, USB Modes

Models and documents

The interactive maps cover 56-pin SSOP and QFN. The 56-ball VFBGA, 100-pin TQFP and 128-pin TQFP use separate pin assignments in Figures 7–8 and 11 of the manufacturer data sheet.

CY7C68013A-56LTXC: Commercial sawn QFN.
CY7C68013A-56LTXCT: Commercial sawn QFN tape and reel.
CY7C68013A-56LTXI: Industrial sawn QFN.

Infineon / Cypress 38-08032 Rev. AD· Pinout Figures 7–11, Table 11, clocking, USB boot and ordering information.
Infineon / Cypress AN15456 Rev. G· USB layout, power architecture and reset supervision.
Infineon FX2LP bypass requirements· Recommended capacitors near the USB transceiver supply pins.
Infineon FX2LP schematic review checklist· Power ramp, reset timing, I²C pull-ups and WAKEUP and RESERVED connections.
Source register· Document revisions, applicable order codes, consulted sections and available file checksums.