ENC28J60 SPI Ethernet controller connection guide

ENC28J60 SPI Ethernet controller SPDIP-28 wiring guide with power, signal assignments, and bench checks.

SPDIP-28

28 contacts Current package

SOIC-28 28 contacts

SSOP-28 28 contacts

QFN-28 29 contacts

Microchip Technology · Skinny through-hole DIP, SP code.

Bring up the 3.3 V core and PHY

Required

Connect every 3.3 V and ground pin. Use a 25 MHz, 3.3 V CMOS source into OSC1 and leave OSC2 open. Provide bypass at each supply pin. Keep Ethernet disconnected during this control-port test.

3.3 V
- VDD (28)
- VDDTX (15)
- VDDRX (19)
- VDDPLL (20)
- VDDOSC (25)
- Current-limited 3.3 V supply
- Clock oscillator supply
- C_VDD.1
- C_VDDTX.1
- C_VDDRX.1
- C_VDDPLL.1
- C_VDDOSC.1
Ground
- VSS (2)
- VSSRX (11)
- VSSTX (18)
- VSSPLL (21)
- VSSOSC (22)
- Supply return
- Oscillator return
- Controller ground
- CV.2
- RBIAS resistor.2
- C_VDD.2
- C_VDDTX.2
- C_VDDRX.2
- C_VDDPLL.2
- C_VDDOSC.2
Regulator output
- VCAP (1)
- CV.1
PHY bias
- RBIAS (14)
- RBIAS resistor.1
25 MHz clock
- OSC1 (23)
- 3.3 V CMOS clock source
Reset control
- RESET (10)
- Controller reset output

Bench checks

With the supply on, check about 2.5 V at VCAP. The clock source must be running before accessing the MAC or PHY.
If the regulator voltage is wrong, power off and inspect VCAP, the ground pins and supply bypass.

Microchip DS39662E, Table 1-1 and §§ 2.1–2.4. Local supply bypass values follow the data sheet.

Connection scenarios

Read the silicon revision over SPI

Use a 3.3 V controller, with SPI mode 0 and 10 MHz clock for this check. Hold CS high between instructions and release hardware reset before SPI transfers.

3.3 V
- VDD (28)
- VDDTX (15)
- VDDRX (19)
- VDDPLL (20)
- VDDOSC (25)
- Current-limited 3.3 V supply
- Clock oscillator supply
- C_VDD.1
- C_VDDTX.1
- C_VDDRX.1
- C_VDDPLL.1
- C_VDDOSC.1
Ground
- VSS (2)
- VSSRX (11)
- VSSTX (18)
- VSSPLL (21)
- VSSOSC (22)
- Supply return
- Oscillator return
- Controller ground
- CV.2
- RBIAS resistor.2
- C_VDD.2
- C_VDDTX.2
- C_VDDRX.2
- C_VDDPLL.2
- C_VDDOSC.2
Regulator output
- VCAP (1)
- CV.1
PHY bias
- RBIAS (14)
- RBIAS resistor.1
25 MHz clock
- OSC1 (23)
- 3.3 V CMOS clock source
Reset control
- RESET (10)
- Controller reset output
Host selects device
- CS (9)
- Controller chip select
Clock
- SCK (8)
- Controller SCK
Host to controller
- SI (7)
- Controller MOSI
Controller to host
- SO (6)
- Controller MISO

Bench checks

Select control-register bank 3 with ECON1.BSEL. Read EREVID at bank address 0x12 with the Read Control Register command.
Check that SO changes only while CS is low and compare the revision byte against the Microchip silicon errata.

Microchip DS39662E, § 4.2 and Register 3-1. Check the silicon errata before using other clock rates.

SPDIP-28 wiring map

Highlighted contacts are used in the required step or selected circuit. Select a contact to inspect it.

Locate the pin 1 mark and use the top view unless the drawing specifies a different view.

Selected pin details

23 · OSC1

Input · Clock inputs / oscillator

Input of the 25 MHz crystal oscillator or external clock.

Microchip DS39662E, Table 1-1

Electrical limits · Pin in the reference

Models and documents

The through-hole, gull-wing and QFN packages have separate mechanical drawings. The QFN pin numbers are shifted and its exposed pad connects to VSS.

ENC28J60-I/SP: Industrial skinny through-hole DIP.

Microchip DS39662E· Table 1-1 pin assignments; § 2 external components; SPI; package and order information.
Microchip ENC28J60 document list· Includes DS80349 silicon errata and packaging resources.
Source register· Document revisions, applicable order codes, consulted sections and available file checksums.