Spark Logic

ENC28J60 SPI Ethernet controller connection guide

ENC28J60 SPI Ethernet controller QFN-28 wiring guide with power, signal assignments, and bench checks.

SPDIP-28 28 contacts
SOIC-28 28 contacts
SSOP-28 28 contacts

QFN-28

29 contacts Current package

Microchip Technology · Leadless QFN, ML code.

Bring up the 3.3 V core and PHY

Required

Connect every 3.3 V and ground pin. Use a 25 MHz, 3.3 V CMOS source into OSC1 and leave OSC2 open. Provide bypass at each supply pin. Keep Ethernet disconnected during this control-port test.

100 nF at VDD between 3.3 V and Ground3.3 V100 nF at VDDGround
100 nF at VDDTX between 3.3 V and Ground3.3 V100 nF at VDDTXGround
100 nF at VDDRX between 3.3 V and Ground3.3 V100 nF at VDDRXGround
100 nF at VDDPLL between 3.3 V and Ground3.3 V100 nF at VDDPLLGround
100 nF at VDDOSC between 3.3 V and Ground3.3 V100 nF at VDDOSCGround
CV 10 µF low ESR between Regulator output and GroundRegulator outputCV 10 µF low ESRGround
RBIAS 2.32 kΩ 1% between PHY bias and GroundPHY biasRBIAS 2.32 kΩ 1%Ground

Bench checks

  • With the supply on, check about 2.5 V at VCAP. The clock source must be running before accessing the MAC or PHY.
  • If the regulator voltage is wrong, power off and inspect VCAP, the ground pins and supply bypass.

Microchip DS39662E, Table 1-1 and §§ 2.1–2.4. Local supply bypass values follow the data sheet.

Connection scenarios

Read the silicon revision over SPI

Use a 3.3 V controller, with SPI mode 0 and 10 MHz clock for this check. Hold CS high between instructions and release hardware reset before SPI transfers.

100 nF at VDD between 3.3 V and Ground3.3 V100 nF at VDDGround
100 nF at VDDTX between 3.3 V and Ground3.3 V100 nF at VDDTXGround
100 nF at VDDRX between 3.3 V and Ground3.3 V100 nF at VDDRXGround
100 nF at VDDPLL between 3.3 V and Ground3.3 V100 nF at VDDPLLGround
100 nF at VDDOSC between 3.3 V and Ground3.3 V100 nF at VDDOSCGround
CV 10 µF low ESR between Regulator output and GroundRegulator outputCV 10 µF low ESRGround
RBIAS 2.32 kΩ 1% between PHY bias and GroundPHY biasRBIAS 2.32 kΩ 1%Ground

Bench checks

  • Select control-register bank 3 with ECON1.BSEL. Read EREVID at bank address 0x12 with the Read Control Register command.
  • Check that SO changes only while CS is low and compare the revision byte against the Microchip silicon errata.

Microchip DS39662E, § 4.2 and Register 3-1. Check the silicon errata before using other clock rates.

QFN-28 wiring map

Highlighted contacts are used in the required step or selected circuit. Select a contact to inspect it.

Locate the pin 1 mark and use the top view unless the drawing specifies a different view.
EP is the exposed center pad on the underside.
Selected pin details

9 · TPIN+

Input · Inputs

Positive input of the Ethernet receive pair.

Microchip DS39662E, Table 1-1

Electrical limits · Pin in the reference

Models and documents

The through-hole, gull-wing and QFN packages have separate mechanical drawings. The QFN pin numbers are shifted and its exposed pad connects to VSS.

ENC28J60-I/ML
Industrial QFN.
ENC28J60T-I/ML
Industrial QFN.