SWD
PA13 is SWDIO and PA14 is SWCLK. NRST lets a compatible probe connect while reset is asserted.
GD32F103 pinout
GD32F103 is a GigaDevice Arm Cortex-M3 microcontroller family. The package map, ordering code and memory layout determine how to connect and configure each device.
128 KiB Flash · 20 KiB SRAM
LQFP48 pinout
LQFP48
29 · PA8
General-purpose port A, bit 8. See the package table for peripheral assignments and input tolerance.
All 48 pins
| Pin | Signal | Direction | Function |
|---|---|---|---|
| 1 | VBAT Supply input | Supply input | RTC and backup-domain supply. In a single-supply design, connect it to VDD with its own bypass capacitor. |
| 2 | PC13 Bidirectional | Bidirectional | General-purpose port C, bit 13. See the package table for peripheral assignments and input tolerance. |
| 3 | PC14 Bidirectional | Bidirectional | GPIO or low-speed external oscillator input (OSC32IN). |
| 4 | PC15 Bidirectional | Bidirectional | GPIO or low-speed external oscillator output (OSC32OUT). |
| 5 | OSCIN Input | Input | High-speed external oscillator input. The internal RC oscillator can start the processor without a crystal. |
| 6 | OSCOUT Output | Output | High-speed external crystal oscillator output. |
| 7 | NRST Bidirectional | Bidirectional | Active-low system reset. Route it to the probe for connection under reset. |
| 8 | VSSA Return | Return | Analog ground. Connect it to the ground plane shared with VSS. |
| 9 | VDDA Supply input | Supply input | Analog supply for the ADC, clock and reset circuitry. Feed it from the VDD supply and bypass it to VSSA. |
| 10 | PA0 Bidirectional | Bidirectional | General-purpose port A, bit 0. See the package table for peripheral assignments and input tolerance. |
| 11 | PA1 Bidirectional | Bidirectional | General-purpose port A, bit 1. See the package table for peripheral assignments and input tolerance. |
| 12 | PA2 Bidirectional | Bidirectional | General-purpose port A, bit 2. See the package table for peripheral assignments and input tolerance. |
| 13 | PA3 Bidirectional | Bidirectional | General-purpose port A, bit 3. See the package table for peripheral assignments and input tolerance. |
| 14 | PA4 Bidirectional | Bidirectional | GPIO and SPI0_NSS in the PA4–PA7 assignment. |
| 15 | PA5 Bidirectional | Bidirectional | GPIO and SPI0_SCK in the PA4–PA7 assignment. |
| 16 | PA6 Bidirectional | Bidirectional | GPIO and SPI0_MISO in the PA4–PA7 assignment. |
| 17 | PA7 Bidirectional | Bidirectional | GPIO and SPI0_MOSI in the PA4–PA7 assignment. |
| 18 | PB0 Bidirectional | Bidirectional | General-purpose port B, bit 0. See the package table for peripheral assignments and input tolerance. |
| 19 | PB1 Bidirectional | Bidirectional | General-purpose port B, bit 1. See the package table for peripheral assignments and input tolerance. |
| 20 | PB2 Bidirectional | Bidirectional | GPIO and BOOT1 strap. BOOT0 low selects main Flash regardless of BOOT1. |
| 21 | PB10 Bidirectional | Bidirectional | General-purpose port B, bit 10. See the package table for peripheral assignments and input tolerance. |
| 22 | PB11 Bidirectional | Bidirectional | General-purpose port B, bit 11. See the package table for peripheral assignments and input tolerance. |
| 23 | VSS_1 Return | Return | Digital ground. Connect every VSS lead to the ground plane. |
| 24 | VDD_1 Supply input | Supply input | Digital supply. Connect every VDD lead and place a local 100 nF bypass at each supply pair. |
| 25 | PB12 Bidirectional | Bidirectional | General-purpose port B, bit 12. See the package table for peripheral assignments and input tolerance. |
| 26 | PB13 Bidirectional | Bidirectional | General-purpose port B, bit 13. See the package table for peripheral assignments and input tolerance. |
| 27 | PB14 Bidirectional | Bidirectional | General-purpose port B, bit 14. See the package table for peripheral assignments and input tolerance. |
| 28 | PB15 Bidirectional | Bidirectional | General-purpose port B, bit 15. See the package table for peripheral assignments and input tolerance. |
| 29 | PA8 Bidirectional | Bidirectional | General-purpose port A, bit 8. See the package table for peripheral assignments and input tolerance. |
| 30 | PA9 Bidirectional | Bidirectional | GPIO and USART0 transmit. Select the USART0 assignment before driving the line as TX. |
| 31 | PA10 Bidirectional | Bidirectional | GPIO and USART0 receive. Select the USART0 assignment to receive on this line. |
| 32 | PA11 Bidirectional | Bidirectional | General-purpose port A, bit 11. See the package table for peripheral assignments and input tolerance. |
| 33 | PA12 Bidirectional | Bidirectional | General-purpose port A, bit 12. See the package table for peripheral assignments and input tolerance. |
| 34 | PA13 Bidirectional | Bidirectional | Serial Wire Debug data (SWDIO). Reserve this signal while using the debug port. |
| 35 | VSS_2 Return | Return | Digital ground. Connect every VSS lead to the ground plane. |
| 36 | VDD_2 Supply input | Supply input | Digital supply. Connect every VDD lead and place a local 100 nF bypass at each supply pair. |
| 37 | PA14 Input in SWD mode | Input in SWD mode | Serial Wire Debug clock (SWCLK). The probe drives this line. |
| 38 | PA15 Bidirectional | Bidirectional | General-purpose port A, bit 15. See the package table for peripheral assignments and input tolerance. |
| 39 | PB3 Bidirectional | Bidirectional | General-purpose port B, bit 3. See the package table for peripheral assignments and input tolerance. |
| 40 | PB4 Bidirectional | Bidirectional | General-purpose port B, bit 4. See the package table for peripheral assignments and input tolerance. |
| 41 | PB5 Bidirectional | Bidirectional | General-purpose port B, bit 5. See the package table for peripheral assignments and input tolerance. |
| 42 | PB6 Bidirectional | Bidirectional | GPIO and I2C0_SCL in the PB6/PB7 assignment. |
| 43 | PB7 Bidirectional | Bidirectional | GPIO and I2C0_SDA in the PB6/PB7 assignment. |
| 44 | BOOT0 Input | Input | Sampled at reset. Hold low for normal execution from main Flash. |
| 45 | PB8 Bidirectional | Bidirectional | General-purpose port B, bit 8. See the package table for peripheral assignments and input tolerance. |
| 46 | PB9 Bidirectional | Bidirectional | General-purpose port B, bit 9. See the package table for peripheral assignments and input tolerance. |
| 47 | VSS_3 Return | Return | Digital ground. Connect every VSS lead to the ground plane. |
| 48 | VDD_3 Supply input | Supply input | Digital supply. Connect every VDD lead and place a local 100 nF bypass at each supply pair. |
Signal assignments
USART0 on PA9/PA10
PA9 transmits to the remote receiver. PA10 receives from the remote transmitter. Use the asynchronous two-wire mode for a basic console.
SPI0 on PA4–PA7
PA4 is NSS, PA5 is clock, PA6 is MISO and PA7 is MOSI. Match the peripheral’s clock polarity, phase, chip select and voltage before exchanging data.
I²C0 on PB6/PB7
PB6 is SCL and PB7 is SDA. Use open-drain operation and pull both lines to the common logic rail. Size the pull-ups for bus capacitance and rise time.
Electrical limits
| Parameter | Limit | Conditions and source |
|---|---|---|
| Flash organization128 KiB code / 0 KiB data | 128 KiB code / 0 KiB data | Flash is distinct from SRAM. Check the memory mapping before assigning linker regions. GD32F103xx datasheet Rev. 3.3, Table 2-1 |
| Serial peripherals3 USART, 2 SPI, 2 I²C, 1 CAN, 1 USBD | 3 USART, 2 SPI, 2 I²C, 1 CAN, 1 USBD | These are peripheral counts. Each interface assignment still depends on the available package pins. GD32F103xx datasheet Rev. 3.3, Table 2-1 |
| ROM serial bootUSART0 | USART0 | USART0 uses PA9/PA10. For codes that support it, USART1 uses PA2/PA3. GD32F103xx datasheet Rev. 3.3, §3.4 |
| VDD and VDDA2.6–3.6 V | 2.6–3.6 V | Use the same source for the digital and analog rails. 3.3 V is the nominal test supply. GD32F103xx datasheet Rev. 3.3, Table 4-2 |
| VBAT1.8–3.6 V | 1.8–3.6 V | Backup-domain supply. Connect to VDD in the single-supply circuit. GD32F103xx datasheet Rev. 3.3, §3.3 |
| Maximum HCLK108 MHz | 108 MHz | Follow the clock-tree and bus prescaler limits separately. GD32F103xx datasheet Rev. 3.3, Table 4-3 |
Models and documents
Interactive maps cover LQFP48, LQFP64 and LQFP100. See Figures 2-3 and 2-7 of the datasheet for LQFP144 and QFN36. Match the suffix on the chip. Board headers and regulator connections depend on the PCB.
- GD32F103C4T6
- 16 KiB Flash · 6 KiB SRAM
- GD32F103C6T6
- 32 KiB Flash · 10 KiB SRAM
- GD32F103C8T6
- 64 KiB Flash · 20 KiB SRAM
- GD32F103CBT6
- 128 KiB Flash · 20 KiB SRAM
- GD32F103xx datasheet Rev. 3.3· Figures 2-4 to 2-6, pin tables 2-6 to 2-8, Figure 4-1 and ordering information.
- GD32F10x user manual Rev. 2.9· Boot modes, GPIO alternate functions and serial-wire debug.
- Source register· Document applicability, revisions and SHA-256 checksums.