Spark Logic

MX25U4033EZBI-12G connection guide

MX25U4033EZBI-12G (USON-8 (4 × 3)) connection guide. Power, ground and chip select. Single SPI and identification.

SOP-8 8 contacts
USON-8 (4 × 4) 9 contacts

USON-8 (4 × 3)

9 contacts Current package
WSON-8 (6 × 5) 9 contacts
WLCSP-8 8 contacts

Macronix · 0.80 mm land pitch · Macronix outline p. 66

Power, ground and chip select

Required

Use a regulated 1.8 V supply and a host with compatible 1.8 V I/O. If the host uses 3.3 V or 5 V, use a level translator that meets the flash and host thresholds, speed and lane direction requirements. A supply adapter alone does not translate signals.

With power off, connect common ground and place C1 (100 nF ceramic) close to VCC and GND. R1 (10 kΩ) is an example pull-up from CS# to flash VCC; the host still drives CS# during transfers.

Leave the exposed metal floating or connect it to the same ground as pin 4. Avoid routing traces or placing vias directly under the pad. Pin 4 remains the required GND terminal.

  • 1.8 V
    • Regulator output
    • C1.1
    • R1.1
  • Ground
    • Supply return
    • Host ground
    • C1.2
  • CS# idle bias
    • →
    • R1.2
C1 · 100 nF between 1.8 V and Ground1.8 VC1 · 100 nFGround
R1 · 10 kΩ between 1.8 V and CS# idle bias1.8 VR1 · 10 kΩCS# idle bias

Bench checks

  • Measure 1.65–2.00 V across the flash supply pins. Budget at least 25 mA for flash program and erase current, plus other loads on the rail.
  • With the host outputs high impedance during supply transitions, check that CS# follows VCC. Wait at least 300 µs after VCC reaches 1.65 V before selecting the flash. Avoid driving any flash line from a powered host while flash power is off.

Macronix PM1755 rev. 1.9 · §§3–4, 11, 13–14 and Tables 13, 15. The 10 kΩ pull-up is an example value.

Connection scenarios

Single SPI and identification

CS# and SCLK are host outputs; MOSI feeds SI and SO drives MISO. With QE = 0, keep WP# and HOLD# high when unused.

Complete the required power step first.

For a dedicated non-quad design, verify QE = 0. If WP# and HOLD# are unused, their internal pull-high circuits are available; optional 10 kΩ pull-ups give defined external bias.

Single SPI and identification · signal wiring (see required power step for supply and bias)1.8 V hostMX25U4033ECS#CS#SCLKSCLKMOSISI/SIO0MISOSO/SIO1Common ground
  • CS#
    • Host CS#
    • →
  • SCLK
    • Host SCLK
    • →
  • SI/SIO0
    • Host MOSI
  • SO/SIO1
    • Host MISO
  • Ground
    • Host ground

Bench checks

  • Start at 1 MHz in mode 0 (or mode 3), MSB first. Keep CS# low for 9Fh and all three response bytes. Expect C2 25 33.
  • Read with 03h and a 24-bit address, MSB first, without dummy clocks. The main array spans 000000h–07FFFFh.
  • On an isolated scratch sector only: erase before reprogramming, issue WREN before each program or erase command, poll WIP with a timeout, then read back. Split writes at 256-byte page boundaries.

Macronix PM1755 rev. 1.9 · §§8–10 and Table 14; Figs. 16–22 for identification and read sequences.

USON-8 (4 × 3) wiring map

External wiring example · Single SPI and identification

Highlighted contacts are used in the required step or selected circuit. Select a contact to highlight its wiring nets.

USON-8 (4 × 3) · Top view (marking side) · index at pin 1.
Dashed outline shows the underside pad schematically. See the package drawing for the footprint.
Selected pin details

4 · GND

Reference · Ground

Required supply return and logic reference. Connect to host and supply ground.

Macronix PM1755 rev. 1.9 · §§3–4, 8–10

Connected nets

Electrical limits · Pin in the reference

Models and documents

PM1755 rev. 1.9 lists five orderable package codes: M1, ZU, ZB, ZN and BA. Select the actual package before wiring; USON and WSON exposed-metal rules differ.

MX25U4033EZBI-12G
USON-8 (4 × 3) · −40 to +85 °C · speed code 12 (command-dependent limits) · RoHS compliant and halogen-free.