Spark Logic

MX25U4033EZUI-12G connection guide

MX25U4033EZUI-12G (USON-8 (4 × 4)) connection guide. Power, ground and chip select. Single SPI and identification.

SOP-8 8 contacts

USON-8 (4 × 4)

9 contacts Current package
USON-8 (4 × 3) 9 contacts
WSON-8 (6 × 5) 9 contacts
WLCSP-8 8 contacts

Macronix · 0.80 mm land pitch · Macronix outline p. 65

Power, ground and chip select

Required

Use a regulated 1.8 V supply and a host with compatible 1.8 V I/O. If the host uses 3.3 V or 5 V, use a level translator that meets the flash and host thresholds, speed and lane direction requirements. A supply adapter alone does not translate signals.

With power off, connect common ground and place C1 (100 nF ceramic) close to VCC and GND. R1 (10 kΩ) is an example pull-up from CS# to flash VCC; the host still drives CS# during transfers.

Keep the exposed metal clear of PCB copper, including traces and pads. Maintain at least 0.2 mm separation from the terminals. Use pin 4 for GND.

  • 1.8 V
    • Regulator output
    • C1.1
    • R1.1
  • Ground
    • Supply return
    • Host ground
    • C1.2
  • CS# idle bias
    • →
    • R1.2
C1 · 100 nF between 1.8 V and Ground1.8 VC1 · 100 nFGround
R1 · 10 kΩ between 1.8 V and CS# idle bias1.8 VR1 · 10 kΩCS# idle bias

Bench checks

  • Measure 1.65–2.00 V across the flash supply pins. Budget at least 25 mA for flash program and erase current, plus other loads on the rail.
  • With the host outputs high impedance during supply transitions, check that CS# follows VCC. Wait at least 300 µs after VCC reaches 1.65 V before selecting the flash. Avoid driving any flash line from a powered host while flash power is off.

Macronix PM1755 rev. 1.9 · §§3–4, 11, 13–14 and Tables 13, 15. The 10 kΩ pull-up is an example value.

Connection scenarios

USON-8 (4 × 4) wiring map

External wiring example · Power, ground and chip select

Highlighted contacts are used in the required step or selected circuit. Select a contact to highlight its wiring nets.

USON-8 (4 × 4) · Top view (marking side) · index at pin 1.
Dashed outline shows the underside pad schematically. See the package drawing for the footprint.
Selected pin details

3 · WP#/SIO2

Input / bidirectional · Bidirectional

With QE = 0, a low level can lock status-register writes when SRWD = 1 in BP protection mode; it does not by itself protect the whole array. With QE = 1, use as SIO2. Internally pulled high in its control role.

Macronix PM1755 rev. 1.9 · §§3–4, 8–10

Electrical limits · Pin in the reference

Models and documents

PM1755 rev. 1.9 lists five orderable package codes: M1, ZU, ZB, ZN and BA. Select the actual package before wiring; USON and WSON exposed-metal rules differ.

MX25U4033EZUI-12G
USON-8 (4 × 4) · −40 to +85 °C · speed code 12 (command-dependent limits) · RoHS compliant and halogen-free.