Spark Logic

MX25U4033EBAI-12G connection guide

MX25U4033EBAI-12G (WLCSP-8) connection guide. Power, ground and chip select. Single SPI and identification.

SOP-8 8 contacts
USON-8 (4 × 4) 9 contacts
USON-8 (4 × 3) 9 contacts
WSON-8 (6 × 5) 9 contacts

WLCSP-8

8 contacts Current package

Macronix · 0.50 mm ball pitch · 0.25 mm ball diameter · Macronix outline p. 68

Power, ground and chip select

Required

Use a regulated 1.8 V supply and a host with compatible 1.8 V I/O. If the host uses 3.3 V or 5 V, use a level translator that meets the flash and host thresholds, speed and lane direction requirements. A supply adapter alone does not translate signals.

With power off, connect common ground and place C1 (100 nF ceramic) close to VCC and GND. R1 (10 kΩ) is an example pull-up from CS# to flash VCC; the host still drives CS# during transfers.

  • 1.8 V
    • Regulator output
    • C1.1
    • R1.1
  • Ground
    • Supply return
    • Host ground
    • C1.2
  • CS# idle bias
    • →
    • R1.2
C1 · 100 nF between 1.8 V and Ground1.8 VC1 · 100 nFGround
R1 · 10 kΩ between 1.8 V and CS# idle bias1.8 VR1 · 10 kΩCS# idle bias

Bench checks

  • Measure 1.65–2.00 V across the flash supply pins. Budget at least 25 mA for flash program and erase current, plus other loads on the rail.
  • With the host outputs high impedance during supply transitions, check that CS# follows VCC. Wait at least 300 µs after VCC reaches 1.65 V before selecting the flash. Avoid driving any flash line from a powered host while flash power is off.

Macronix PM1755 rev. 1.9 · §§3–4, 11, 13–14 and Tables 13, 15. The 10 kΩ pull-up is an example value.

Connection scenarios

Quad I/O read

Route all four SIO lines to bidirectional host pins. WP#/SIO2 and HOLD#/SIO3 must be free to drive and be driven; do not strap them to a rail. QE disables the hardware WP# and HOLD# functions.

Complete the required power step first.

Quad I/O read · signal wiring (see required power step for supply and bias)1.8 V hostMX25U4033ECS#CS#SCLKSCLKIO0SI/SIO0IO1SO/SIO1IO2WP#/SIO2IO3HOLD#/SIO3Common ground
  • CS#
    • Host CS#
    • →
  • SCLK
    • Host SCLK
    • →
  • SI/SIO0
    • Host IO0
  • SO/SIO1
    • Host IO1
  • WP#/SIO2
    • Host IO2
  • HOLD#/SIO3
    • Host IO3
  • Ground
    • Host ground

Bench checks

  • First confirm single SPI communication. Read the status register (05h), issue WREN (06h) and write it with QE (bit 6) set via WRSR (01h), preserving the intended protection bits. Poll WIP and verify QE. QE is nonvolatile, so read it on an unknown part.
  • Use 4READ (EBh) in 1-4-4 mode: send the opcode on SIO0, the 24-bit address over four lines, then two mode clocks (for example 00h for standalone reads) and four dummy clocks. Release the host data outputs before data returns.
  • Compare returned bytes with 03h at the same address. 4READ is rated up to 70 MHz under Table 14 conditions.

Macronix PM1755 rev. 1.9 · §§8–10 and Table 14; Figs. 16–22 for identification and read sequences.

WLCSP-8 wiring map

External wiring example · Quad I/O read

Highlighted contacts are used in the required step or selected circuit. Select a contact to highlight its wiring nets.

12 A B C D
Top view through the package · A1 at upper left; the solder-ball side is mirrored.
Selected pin details

B1 · HOLD#/SIO3

Input / bidirectional · Bidirectional

With QE = 0, an active-low pause while CS# is low. Change HOLD# with SCLK low for immediate entry or exit. With QE = 1, use as SIO3. Internally pulled high in its control role.

Macronix PM1755 rev. 1.9 · §§3–4, 8–10

Connected nets

Electrical limits · Pin in the reference

Models and documents

PM1755 rev. 1.9 lists five orderable package codes: M1, ZU, ZB, ZN and BA. Select the actual package before wiring; USON and WSON exposed-metal rules differ.

MX25U4033EBAI-12G
WLCSP-8 · −40 to +85 °C · speed code 12 (command-dependent limits) · RoHS compliant and halogen-free.