Selected device: STM32F100RE (512 KiB Flash, 32 KiB SRAM). The guide uses a regulated 3.3 V supply and lists the physical pin numbers for this package.
Connect every VDD and VSS pin
Required
Connect every VDD to one regulated 3.3 V rail and every VSS to board ground. The digital supply operating range is 2.0–3.6 V. Complete the VDDA and VBAT steps before powering the MCU.
Install 4 ceramic 100 nF capacitors, one close to each VDD/VSS pair (#19/#18, #32/#31, #48/#47, #64/#63). Place the bulk capacitor across VDD_3 #64 and VSS_3 #63. Choose a part that still provides 4.7 µF or more after tolerance and DC bias.
Check the connection
With power off, check that each VDD and VSS pin connects to its intended rail. After completing the power and boot steps, measure 3.2–3.4 V between each VDD and board ground with the supply on.
Sources: DS5944 Rev 11 · power supply scheme, Figure 9·AN2586 Rev 8 · decoupling, §2.2·AN2586 Rev 8 · decoupling layout, Figure 13
Power the analog domain
Required
Connect VDDA to the same 3.3 V rail as VDD and VSSA to board ground, even when neither converter is used. With the ADC or DAC enabled, the VDDA operating range is 2.4–3.6 V.
The analog reference is internally bonded to VDDA and VSSA in this package.
Place 10 nF and 1 µF ceramic capacitors in parallel close to the analog power pins.
Check the connection
After completing the required wiring, power the board and measure VDDA with the meter common lead on VSSA. Expect 3.2–3.4 V.
Sources: DS5944 Rev 11 · power supply scheme, Figure 9·DS5944 Rev 11 · shared reference decoupling, Figure 36
Connect VBAT to the main supply
Required
For a design powered only by the main supply, connect VBAT to VDD and fit one 100 nF ceramic capacitor from VBAT to board ground close to the pin.
The real-time clock and backup registers lose power when the main supply is removed. If you need separate backup power, use the VBAT operating range of 1.8–3.6 V and review the startup current-injection conditions in RM0041 §4.1.2.
Check the connection
With the board unpowered, verify continuity between VBAT and VDD. After completing the required wiring, power the board and measure 3.2–3.4 V at VBAT relative to board ground.
Sources: AN2586 Rev 8 · VBAT decoupling, §2.2·RM0041 Rev 6 · battery backup domain, §4.1.2
Pins for this step
- VBAT
- #1
Select the boot memory
Required
User Flash
With power off, connect BOOT0 to ground through 10 kΩ. Either BOOT1 level selects user Flash while BOOT0 is low.
Use ±5%, ⅛ W resistors. Even with the full 3.4 V across a resistor at its 9.5 kΩ minimum, dissipation is below 1.3 mW. The MCU samples the straps after reset and when exiting Standby.
Check the connection
Measure BOOT0 near 0 V relative to board ground at reset release. If valid firmware is present, it should run from user Flash.
Pins for this step
- BOOT0
- #60
System bootloader
With power off, connect BOOT0 to VDD through 10 kΩ and PB2 (BOOT1) to ground through a second 10 kΩ resistor.
Use ±5%, ⅛ W resistors. Even with the full 3.4 V across a resistor at its 9.5 kΩ minimum, dissipation is below 1.3 mW. The MCU samples the straps after reset and when exiting Standby.
For the STM32F100 system bootloader, follow the default USART1 wiring on PA9/PA10. After programming, restore the user Flash strap and reset.
Check the connection
Measure BOOT0 near VDD and PB2 near 0 V relative to board ground at reset release. The device should select system memory.
Sources: AN2586 Rev 8 · boot straps, Table 2 and Figure 10·AN2606 Rev 68 · system bootloader pins, Table 36
Add a reset noise filter
Optional
With the board unpowered, place a 100 nF ceramic capacitor between NRST and board ground to filter reset noise. The MCU supplies its own reset pull-up.
If an external circuit asserts reset, use a switch to ground or an open-drain output that releases the line after the reset pulse.
Check the connection
Measure NRST relative to board ground with the board powered. Expect near VDD when released and near 0 V while external reset is asserted.
Pins for this step
- NRST
- #7
Connect a serial wire debug probe
Optional
Connect SWDIO to PA13 and SWCLK to PA14. Connect probe ground to board ground and, if the probe has a target voltage reference input (VTref), connect it to the VDD rail according to the probe manual. Power the target from its own supply.
If supported, connect the probe reset output to NRST for connect-under-reset. Reserve PA13 and PA14 for debug in firmware while you need SWD.
Check the connection
With the target powered, measure VTref relative to probe ground where available. Expect the same voltage as VDD. Select SWD in the debugger and confirm that it detects the target.
Sources: AN2586 Rev 8 · debug pin assignments, Tables 3–4·AN2586 Rev 8 · debug connector, Figure 12
Connect a 3.3 V serial adapter
Optional
Default · PA9 / PA10
Use a serial adapter with 3.3 V TTL/CMOS signal levels. Keep RS-232 and 5 V logic disconnected. Power the target from its own 3.3 V supply and leave the adapter VCC pin open.
Wire adapter TX to PA10 #43 (MCU RX), adapter RX to PA9 #42 (MCU TX), and adapter GND to board ground. Power both ends before transmitting.
In application firmware, enable the GPIO, AFIO and USART1 clocks. Select AFIO_MAPR.USART1_REMAP = 0, configure TX as alternate-function push-pull and RX as an input, and set the same baud rate and framing on both ends. This circuit uses asynchronous mode without hardware flow control.
PA9 and PA10 also carry TIM1_CH2/TIM1_CH3 and the TIM15_BKIN/TIM17_BKIN break inputs. Use the remap if another peripheral already uses these pins.
For the system bootloader, use PA9/PA10 and the STM32 programming tool. The remap applies to your own firmware.
Check the connection
With a test application on the MCU, open a terminal with matching settings, for example 115200 baud, 8 data bits, no parity and 1 stop bit. Send a byte and confirm that the application echoes it. If the terminal stays silent, verify the crossed TX/RX wiring, common ground and selected remap.
Sources: RM0041 Rev 6 · USART1 remapping, Table 44·DS5944 Rev 11 · pin definitions, Table 4·AN2606 Rev 68 · system bootloader pins, Table 36
Remap · PB6 / PB7
Use a serial adapter with 3.3 V TTL/CMOS signal levels. Keep RS-232 and 5 V logic disconnected. Power the target from its own 3.3 V supply and leave the adapter VCC pin open.
Wire adapter TX to PB7 #59 (MCU RX), adapter RX to PB6 #58 (MCU TX), and adapter GND to board ground. Power both ends before transmitting.
In application firmware, enable the GPIO, AFIO and USART1 clocks. Select AFIO_MAPR.USART1_REMAP = 1, configure TX as alternate-function push-pull and RX as an input, and set the same baud rate and framing on both ends. This circuit uses asynchronous mode without hardware flow control.
PB6/PB7 share the default I²C1 clock and data lines and the TIM16_CH1N/TIM17_CH1N outputs. They also carry TIM4_CH1/TIM4_CH2. Use the default USART1 pins if PB6/PB7 are occupied. If I²C1 is the only conflict, move it to PB8/PB9 when those pins are free.
For the system bootloader, use PA9/PA10 and the STM32 programming tool. The remap applies to your own firmware.
Check the connection
With a test application on the MCU, open a terminal with matching settings, for example 115200 baud, 8 data bits, no parity and 1 stop bit. Send a byte and confirm that the application echoes it. If the terminal stays silent, verify the crossed TX/RX wiring, common ground and selected remap.
Sources: RM0041 Rev 6 · USART1 remapping, Table 44·DS5944 Rev 11 · pin definitions, Table 4·AN2606 Rev 68 · system bootloader pins, Table 36
Reference documents
- Datasheet for STM32F100xC/xD/xE· ST DS5944 Rev 11 · PDF
- Reference manual for STM32F100· ST RM0041 Rev 6 · PDF
- Getting started with STM32F10xxx hardware development· ST AN2586 Rev 8 · PDF
- Errata for STM32F100xC/xD/xE· ST ES0136 Rev 7 · PDF · Check the sales type and silicon marking before applying. Table 1 limits this sheet to internal code B and Table 2 lists silicon revision A (REV_ID 0x1000).
- Introduction to system memory boot mode on STM32 MCUs· ST AN2606 Rev 68 · PDF