Spark Logic

STM32F100

LQFP48 7 × 7 mm

LQFP64

10 × 10 mm Current package
LQFP100 14 × 14 mm

Memory options · LQFP64

DeviceFlashSRAM
STM32F100R416 KiB4 KiB
STM32F100R632 KiB4 KiB
STM32F100R864 KiB8 KiB
STM32F100RB128 KiB8 KiB
STM32F100RC256 KiB24 KiB
STM32F100RD384 KiB32 KiB
STM32F100RE512 KiB32 KiB

The physical pins stay in the same positions. Select a device to see its alternate functions and electrical specifications.

Pinout

STM32F100R4 · LQFP64 top view · Start at the pin 1 marker and count counterclockwise.

#1 VBAT Backup supply · 1.8–3.6 V Pin details below ↓
left edge · pin names and signals

Details for the selected pin

#1 VBAT

Backup supply

Powers the RTC, low-speed external oscillator and backup registers when VDD is absent.

VBAT operating range
1.8–3.6 VRelative to VSS. Connect to VDD when a separate backup supply is unused.
VBAT bypass
100 nFAt VBAT when connected to VDD, as shown in the hardware guide. For a separate source check RM0041 §4.1.2 for startup current injection.

The table includes all 64 contacts, even when a diagram filter is active.

Pin list

64 / 64

Open a pin for wiring and electrical details. Dotted underlines indicate a tooltip.

PinPurposeVoltage & limitsSignals
#1 VBAT Powers the RTC, low-speed external oscillator and backup registers when VDD is absent.
VBAT operating range
1.8–3.6 VRelative to VSS. Connect to VDD when a separate backup supply is unused.
 —
#2 PC13 Tamper input or backup-domain GPIO. Backup settings can survive a system reset.
Standard input LOW / HIGH
≤1.16 V / ≥1.84 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Backup-domain GPIO output
2 MHz max · 30 pF maxPC13–PC15 share a 3 mA power switch. Keep these pins from sourcing load current.
Real-time clock (RTC) tamper detection input. Optional RTC calibration, alarm or second output selected by BKP_RTCCR.
#3 PC14 Low-speed external crystal input. Backup settings can survive a system reset.
Standard input LOW / HIGH
≤1.16 V / ≥1.84 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Backup-domain GPIO output
2 MHz max · 30 pF maxPC13–PC15 share a 3 mA power switch. Keep these pins from sourcing load current.
LSE crystal frequency
32.768 kHzCrystal mode. Use the LSE oscillator conditions and the crystal’s load specification.
Low-speed external (LSE) oscillator input for a 32.768 kHz crystal or external clock.
#4 PC15 Low-speed external crystal output. Backup settings can survive a system reset.
Standard input LOW / HIGH
≤1.16 V / ≥1.84 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Backup-domain GPIO output
2 MHz max · 30 pF maxPC13–PC15 share a 3 mA power switch. Keep these pins from sourcing load current.
LSE crystal frequency
32.768 kHzCrystal mode. Use the LSE oscillator conditions and the crystal’s load specification.
Low-speed external (LSE) crystal oscillator output.
#5 OSC_IN High-speed external crystal or bypass clock input. PD0 is available here through AFIO remap with HSE off.
HSE crystal frequency
4–24 MHzCrystal mode. Use oscillator limits and the chosen crystal load parameters.
Remapped Port D GPIO mapped to the oscillator pin when HSE is disabled. AFIO_MAPR.PD01_REMAP = 1; HSE off.
#6 OSC_OUT High-speed external crystal output. PD1 is available here through AFIO remap with HSE off.
HSE crystal frequency
4–24 MHzCrystal mode. Use oscillator limits and the chosen crystal load parameters.
Remapped Port D GPIO mapped to the oscillator pin when HSE is disabled. AFIO_MAPR.PD01_REMAP = 1; HSE off.
#7 NRST Pull low to reset the MCU. Let the internal pull-up release the pin.
Reset input LOW / HIGH
≤0.8 V / ≥2.0 VRelative to VSS. An internal weak pull-up keeps NRST high when released.
 —
#8 PC0 Port C bit 0. Floating input after reset; software selects the GPIO or peripheral mode.
Standard input LOW / HIGH
≤1.16 V / ≥1.84 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
ADC conversion input
VSSA to VDDA12-bit analog mode. VREF− must be at VSSA; on this package the reference pins are bonded to VSSA and VDDA.
External analog input channel 10 of ADC1.
#9 PC1 Port C bit 1. Floating input after reset; software selects the GPIO or peripheral mode.
Standard input LOW / HIGH
≤1.16 V / ≥1.84 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
ADC conversion input
VSSA to VDDA12-bit analog mode. VREF− must be at VSSA; on this package the reference pins are bonded to VSSA and VDDA.
External analog input channel 11 of ADC1.
#10 PC2 Port C bit 2. Floating input after reset; software selects the GPIO or peripheral mode.
Standard input LOW / HIGH
≤1.16 V / ≥1.84 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
ADC conversion input
VSSA to VDDA12-bit analog mode. VREF− must be at VSSA; on this package the reference pins are bonded to VSSA and VDDA.
External analog input channel 12 of ADC1.
#11 PC3 Port C bit 3. Floating input after reset; software selects the GPIO or peripheral mode.
Standard input LOW / HIGH
≤1.16 V / ≥1.84 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
ADC conversion input
VSSA to VDDA12-bit analog mode. VREF− must be at VSSA; on this package the reference pins are bonded to VSSA and VDDA.
External analog input channel 13 of ADC1.
#12 VSSA Analog ground and ADC return. Connect to system ground.
Ground reference
0 VConnect all VSS and VSSA pins to system ground.
 —
#13 VDDA Supply for the analog circuitry, reset blocks and oscillators.
VDDA operating range
2.0–3.6 V · 2.4–3.6 V with ADCRelative to VSSA. Supply VDDA from the same source as VDD.
 —
#14 PA0 Port A bit 0. Floating input after reset; software selects the GPIO or peripheral mode.
Standard input LOW / HIGH
≤1.16 V / ≥1.84 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
ADC conversion input
VSSA to VDDA12-bit analog mode. VREF− must be at VSSA; on this package the reference pins are bonded to VSSA and VDDA.
Standby wake-up input. External analog input channel 0 of ADC1. Timer 2, channel 1 input capture, output compare or pulse-width modulation (PWM), or external trigger input. Universal synchronous/asynchronous receiver/transmitter (USART) 2, clear-to-send input.
#15 PA1 Port A bit 1. Floating input after reset; software selects the GPIO or peripheral mode.
Standard input LOW / HIGH
≤1.16 V / ≥1.84 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
ADC conversion input
VSSA to VDDA12-bit analog mode. VREF− must be at VSSA; on this package the reference pins are bonded to VSSA and VDDA.
External analog input channel 1 of ADC1. Timer 2, channel 2 input capture, output compare or pulse-width modulation (PWM). Universal synchronous/asynchronous receiver/transmitter (USART) 2, request-to-send output.
#16 PA2 Port A bit 2. Floating input after reset; software selects the GPIO or peripheral mode.
Standard input LOW / HIGH
≤1.16 V / ≥1.84 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
ADC conversion input
VSSA to VDDA12-bit analog mode. VREF− must be at VSSA; on this package the reference pins are bonded to VSSA and VDDA.
External analog input channel 2 of ADC1. Timer 2, channel 3 input capture, output compare or pulse-width modulation (PWM). Timer 15, channel 1 input capture, output compare or pulse-width modulation (PWM). Universal synchronous/asynchronous receiver/transmitter (USART) 2, transmit data output.
#17 PA3 Port A bit 3. Floating input after reset; software selects the GPIO or peripheral mode.
Standard input LOW / HIGH
≤1.16 V / ≥1.84 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
ADC conversion input
VSSA to VDDA12-bit analog mode. VREF− must be at VSSA; on this package the reference pins are bonded to VSSA and VDDA.
External analog input channel 3 of ADC1. Timer 2, channel 4 input capture, output compare or pulse-width modulation (PWM). Timer 15, channel 2 input capture, output compare or pulse-width modulation (PWM). Universal synchronous/asynchronous receiver/transmitter (USART) 2, receive data input.
#18 VSS_4 Connect this digital return directly to system ground.
Ground reference
0 VConnect all VSS and VSSA pins to system ground.
 —
#19 VDD_4 Connect this supply pin to VDD and place its bypass capacitor next to the corresponding VSS pin.
VDD operating range
2.0–3.6 VRelative to VSS. Connect every VDD and VSS pin.
 —
#20 PA4 Port A bit 4. Floating input after reset; software selects the GPIO or peripheral mode.
Standard input LOW / HIGH
≤1.16 V / ≥1.84 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
ADC conversion input
VSSA to VDDA12-bit analog mode. VREF− must be at VSSA; on this package the reference pins are bonded to VSSA and VDDA.
Analog output of DAC channel 1. External analog input channel 4 of ADC1. Serial Peripheral Interface (SPI) 1, negative slave select (chip select), input in slave mode or input/output in master mode. Universal synchronous/asynchronous receiver/transmitter (USART) 2, synchronous clock output.
#21 PA5 Port A bit 5. Floating input after reset; software selects the GPIO or peripheral mode.
Standard input LOW / HIGH
≤1.16 V / ≥1.84 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
ADC conversion input
VSSA to VDDA12-bit analog mode. VREF− must be at VSSA; on this package the reference pins are bonded to VSSA and VDDA.
Analog output of DAC channel 2. External analog input channel 5 of ADC1. Serial Peripheral Interface (SPI) 1, serial clock, output in master mode or input in slave mode.
#22 PA6 Port A bit 6. Floating input after reset; software selects the GPIO or peripheral mode.
Standard input LOW / HIGH
≤1.16 V / ≥1.84 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
ADC conversion input
VSSA to VDDA12-bit analog mode. VREF− must be at VSSA; on this package the reference pins are bonded to VSSA and VDDA.
External analog input channel 6 of ADC1. Serial Peripheral Interface (SPI) 1, master in, slave out: data from slave to master. Timer 3, channel 1 input capture, output compare or pulse-width modulation (PWM).
Remapped Timer 1, break input for shutting off timer outputs. AFIO_MAPR.TIM1_REMAP = 01. Timer 16, channel 1 input capture, output compare or pulse-width modulation (PWM). AFIO_MAPR2.TIM16_REMAP = 1.
#23 PA7 Port A bit 7. Floating input after reset; software selects the GPIO or peripheral mode.
Standard input LOW / HIGH
≤1.16 V / ≥1.84 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
ADC conversion input
VSSA to VDDA12-bit analog mode. VREF− must be at VSSA; on this package the reference pins are bonded to VSSA and VDDA.
External analog input channel 7 of ADC1. Serial Peripheral Interface (SPI) 1, master out, slave in: data from master to slave. Timer 3, channel 2 input capture, output compare or pulse-width modulation (PWM).
Remapped Timer 1, channel 1 complementary pulse-width modulation (PWM) output. AFIO_MAPR.TIM1_REMAP = 01. Timer 17, channel 1 input capture, output compare or pulse-width modulation (PWM). AFIO_MAPR2.TIM17_REMAP = 1.
#24 PC4 Port C bit 4. Floating input after reset; software selects the GPIO or peripheral mode.
Standard input LOW / HIGH
≤1.16 V / ≥1.84 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
ADC conversion input
VSSA to VDDA12-bit analog mode. VREF− must be at VSSA; on this package the reference pins are bonded to VSSA and VDDA.
External analog input channel 14 of ADC1.
#25 PC5 Port C bit 5. Floating input after reset; software selects the GPIO or peripheral mode.
Standard input LOW / HIGH
≤1.16 V / ≥1.84 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
ADC conversion input
VSSA to VDDA12-bit analog mode. VREF− must be at VSSA; on this package the reference pins are bonded to VSSA and VDDA.
External analog input channel 15 of ADC1.
#26 PB0 Port B bit 0. Floating input after reset; software selects the GPIO or peripheral mode.
Standard input LOW / HIGH
≤1.16 V / ≥1.84 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
ADC conversion input
VSSA to VDDA12-bit analog mode. VREF− must be at VSSA; on this package the reference pins are bonded to VSSA and VDDA.
External analog input channel 8 of ADC1. Timer 3, channel 3 input capture, output compare or pulse-width modulation (PWM).
Remapped Timer 1, channel 2 complementary pulse-width modulation (PWM) output. AFIO_MAPR.TIM1_REMAP = 01.
#27 PB1 Port B bit 1. Floating input after reset; software selects the GPIO or peripheral mode.
Standard input LOW / HIGH
≤1.16 V / ≥1.84 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
ADC conversion input
VSSA to VDDA12-bit analog mode. VREF− must be at VSSA; on this package the reference pins are bonded to VSSA and VDDA.
External analog input channel 9 of ADC1. Timer 3, channel 4 input capture, output compare or pulse-width modulation (PWM).
Remapped Timer 1, channel 3 complementary pulse-width modulation (PWM) output. AFIO_MAPR.TIM1_REMAP = 01.
#28 PB2 Sampled as BOOT1 with BOOT0 at reset. It can serve as a GPIO after boot selection.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Boot selection
0 → Flash · 1 → System memory or SRAMWith BOOT0 = 1, BOOT1 = 0 selects system memory and BOOT1 = 1 selects SRAM.
After reset Boot mode select input PB2 during reset, in combination with BOOT0.
#29 PB10 Port B bit 10. Floating input after reset; software selects the GPIO or peripheral mode.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Remapped HDMI Consumer Electronics Control. Bidirectional open-drain signaling. AFIO_MAPR2.CEC_REMAP = 1. Timer 2, channel 3 input capture, output compare or pulse-width modulation (PWM). AFIO_MAPR.TIM2_REMAP = 10 or AFIO_MAPR.TIM2_REMAP = 11.
#30 PB11 Port B bit 11. Floating input after reset; software selects the GPIO or peripheral mode.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Remapped Timer 2, channel 4 input capture, output compare or pulse-width modulation (PWM). AFIO_MAPR.TIM2_REMAP = 10 or AFIO_MAPR.TIM2_REMAP = 11.
#31 VSS_1 Connect this digital return directly to system ground.
Ground reference
0 VConnect all VSS and VSSA pins to system ground.
 —
#32 VDD_1 Connect this supply pin to VDD and place its bypass capacitor next to the corresponding VSS pin.
VDD operating range
2.0–3.6 VRelative to VSS. Connect every VDD and VSS pin.
 —
#33 PB12 Port B bit 12. Floating input after reset; software selects the GPIO or peripheral mode.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Timer 1, break input for shutting off timer outputs.
#34 PB13 Port B bit 13. Floating input after reset; software selects the GPIO or peripheral mode.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Timer 1, channel 1 complementary pulse-width modulation (PWM) output.
#35 PB14 Port B bit 14. Floating input after reset; software selects the GPIO or peripheral mode.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Timer 1, channel 2 complementary pulse-width modulation (PWM) output.
Remapped Timer 15, channel 1 input capture, output compare or pulse-width modulation (PWM). AFIO_MAPR2.TIM15_REMAP = 1.
#36 PB15 Port B bit 15. Floating input after reset; software selects the GPIO or peripheral mode.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Timer 1, channel 3 complementary pulse-width modulation (PWM) output. Timer 15, channel 1 complementary pulse-width modulation (PWM) output.
Remapped Timer 15, channel 2 input capture, output compare or pulse-width modulation (PWM). AFIO_MAPR2.TIM15_REMAP = 1.
#37 PC6 Port C bit 6. Floating input after reset; software selects the GPIO or peripheral mode.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Remapped Timer 3, channel 1 input capture, output compare or pulse-width modulation (PWM). AFIO_MAPR.TIM3_REMAP = 11.
#38 PC7 Port C bit 7. Floating input after reset; software selects the GPIO or peripheral mode.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Remapped Timer 3, channel 2 input capture, output compare or pulse-width modulation (PWM). AFIO_MAPR.TIM3_REMAP = 11.
#39 PC8 Port C bit 8. Floating input after reset; software selects the GPIO or peripheral mode.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Remapped Timer 3, channel 3 input capture, output compare or pulse-width modulation (PWM). AFIO_MAPR.TIM3_REMAP = 11.
#40 PC9 Port C bit 9. Floating input after reset; software selects the GPIO or peripheral mode.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Remapped Timer 3, channel 4 input capture, output compare or pulse-width modulation (PWM). AFIO_MAPR.TIM3_REMAP = 11.
#41 PA8 Port A bit 8. Floating input after reset; software selects the GPIO or peripheral mode.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Microcontroller clock output. Timer 1, channel 1 input capture, output compare or pulse-width modulation (PWM). Universal synchronous/asynchronous receiver/transmitter (USART) 1, synchronous clock output.
#42 PA9 Port A bit 9. Floating input after reset; software selects the GPIO or peripheral mode.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Timer 1, channel 2 input capture, output compare or pulse-width modulation (PWM). Timer 15, break input for shutting off timer outputs. Universal synchronous/asynchronous receiver/transmitter (USART) 1, transmit data output.
#43 PA10 Port A bit 10. Floating input after reset; software selects the GPIO or peripheral mode.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Timer 1, channel 3 input capture, output compare or pulse-width modulation (PWM). Timer 17, break input for shutting off timer outputs. Universal synchronous/asynchronous receiver/transmitter (USART) 1, receive data input.
#44 PA11 Port A bit 11. Floating input after reset; software selects the GPIO or peripheral mode.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Timer 1, channel 4 input capture, output compare or pulse-width modulation (PWM). Universal synchronous/asynchronous receiver/transmitter (USART) 1, clear-to-send input.
#45 PA12 Port A bit 12. Floating input after reset; software selects the GPIO or peripheral mode.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Timer 1, external trigger input. Universal synchronous/asynchronous receiver/transmitter (USART) 1, request-to-send output.
#46 PA13 JTAG mode select or Serial Wire Debug data with an internal pull-up after reset.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
After reset Joint Test Action Group (JTAG) test mode select / Serial Wire Debug (SWD) bidirectional data line.
#47 VSS_2 Connect this digital return directly to system ground.
Ground reference
0 VConnect all VSS and VSSA pins to system ground.
 —
#48 VDD_2 Connect this supply pin to VDD and place its bypass capacitor next to the corresponding VSS pin.
VDD operating range
2.0–3.6 VRelative to VSS. Connect every VDD and VSS pin.
 —
#49 PA14 JTAG or Serial Wire Debug clock input with an internal pull-down after reset.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
After reset JTAG test clock / Serial Wire Debug (SWD) clock input.
#50 PA15 JTAG test data input with an internal pull-up after reset.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
After reset JTAG test data input.
Remapped Serial Peripheral Interface (SPI) 1, negative slave select (chip select), input in slave mode or input/output in master mode. AFIO_MAPR.SPI1_REMAP = 1. Timer 2, channel 1 input capture, output compare or pulse-width modulation (PWM), or external trigger input. AFIO_MAPR.TIM2_REMAP = 01 or AFIO_MAPR.TIM2_REMAP = 11.
#51 PC10 Port C bit 10. Floating input after reset; software selects the GPIO or peripheral mode.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
 —
#52 PC11 Port C bit 11. Floating input after reset; software selects the GPIO or peripheral mode.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
 —
#53 PC12 Port C bit 12. Floating input after reset; software selects the GPIO or peripheral mode.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
 —
#54 PD2 Port D bit 2. Floating input after reset; software selects the GPIO or peripheral mode.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Timer 3, external trigger input.
#55 PB3 JTAG test data output after reset. Optional asynchronous trace output.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
After reset JTAG test data output.
Remapped Serial Peripheral Interface (SPI) 1, serial clock, output in master mode or input in slave mode. AFIO_MAPR.SPI1_REMAP = 1. Timer 2, channel 2 input capture, output compare or pulse-width modulation (PWM). AFIO_MAPR.TIM2_REMAP = 01 or AFIO_MAPR.TIM2_REMAP = 11. Serial Wire Output for asynchronous trace data. AFIO_MAPR.SWJ_CFG = 010; enable asynchronous trace.
#56 PB4 Active-low JTAG test reset input with an internal pull-up after reset.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
After reset Active-low JTAG test reset input.
Remapped Serial Peripheral Interface (SPI) 1, master in, slave out: data from slave to master. AFIO_MAPR.SPI1_REMAP = 1. Timer 3, channel 1 input capture, output compare or pulse-width modulation (PWM). AFIO_MAPR.TIM3_REMAP = 10.
#57 PB5 Port B bit 5. Floating input after reset; software selects the GPIO or peripheral mode.
Standard input LOW / HIGH
≤1.16 V / ≥1.84 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Inter-Integrated Circuit (I²C) 1, System Management Bus (SMBus) alert line. Timer 16, break input for shutting off timer outputs.
Remapped Serial Peripheral Interface (SPI) 1, master out, slave in: data from master to slave. AFIO_MAPR.SPI1_REMAP = 1. Timer 3, channel 2 input capture, output compare or pulse-width modulation (PWM). AFIO_MAPR.TIM3_REMAP = 10.
#58 PB6 Port B bit 6. Floating input after reset; software selects the GPIO or peripheral mode.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Inter-Integrated Circuit (I²C) 1, open-drain clock line. Use an external pull-up. Timer 16, channel 1 complementary pulse-width modulation (PWM) output.
Remapped Universal synchronous/asynchronous receiver/transmitter (USART) 1, transmit data output. AFIO_MAPR.USART1_REMAP = 1.
#59 PB7 Port B bit 7. Floating input after reset; software selects the GPIO or peripheral mode.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Inter-Integrated Circuit (I²C) 1, open-drain data line. Use an external pull-up. Timer 17, channel 1 complementary pulse-width modulation (PWM) output.
Remapped Universal synchronous/asynchronous receiver/transmitter (USART) 1, receive data input. AFIO_MAPR.USART1_REMAP = 1.
#60 BOOT0 Keep low at reset for normal flash boot. Set high only with the required PB2/BOOT1 level.
Boot selection
0 → Flash · 1 → System memory or SRAMWith BOOT0 = 1, BOOT1 = 0 selects system memory and BOOT1 = 1 selects SRAM.
 —
#61 PB8 Port B bit 8. Floating input after reset; software selects the GPIO or peripheral mode.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
HDMI Consumer Electronics Control. Bidirectional open-drain signaling. Timer 16, channel 1 input capture, output compare or pulse-width modulation (PWM).
Remapped Inter-Integrated Circuit (I²C) 1, open-drain clock line. Use an external pull-up. AFIO_MAPR.I2C1_REMAP = 1.
#62 PB9 Port B bit 9. Floating input after reset; software selects the GPIO or peripheral mode.
FT input LOW / HIGH
≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Timer 17, channel 1 input capture, output compare or pulse-width modulation (PWM).
Remapped Inter-Integrated Circuit (I²C) 1, open-drain data line. Use an external pull-up. AFIO_MAPR.I2C1_REMAP = 1.
#63 VSS_3 Connect this digital return directly to system ground.
Ground reference
0 VConnect all VSS and VSSA pins to system ground.
 —
#64 VDD_3 Connect this supply pin to VDD and place its bypass capacitor next to the corresponding VSS pin.
VDD operating range
2.0–3.6 VRelative to VSS. Connect every VDD and VSS pin.
 —

Interface mappings

Choose one mapping per peripheral, then check that another enabled interface does not use the same pads. Preserve SWD on PA13 and PA14 if you need a debugger.

A dash marks a signal whose pad is unavailable in this package. A clock, select or flow control line is only needed in the modes described for that signal.

Check two mappings for shared pins
CEC · 2 mappings

Default

AFIO_MAPR2.CEC_REMAP = 0

  • HDMI Consumer Electronics Control. Bidirectional open-drain signaling. Bidirectional open drain #61 PB8

↪ Remap

AFIO_MAPR2.CEC_REMAP = 1

  • HDMI Consumer Electronics Control. Bidirectional open-drain signaling. Bidirectional open drain #29 PB10
I2C1 · 2 mappings

Default

AFIO_MAPR.I2C1_REMAP = 0

  • Inter-Integrated Circuit (I²C) 1, open-drain clock line. Use an external pull-up. Bidirectional open drain #58 PB6
  • Inter-Integrated Circuit (I²C) 1, open-drain data line. Use an external pull-up. Bidirectional open drain #59 PB7
  • Inter-Integrated Circuit (I²C) 1, System Management Bus (SMBus) alert line. Open-drain SMBus alert #57 PB5

↪ Remap

AFIO_MAPR.I2C1_REMAP = 1

PB8 is also the default HDMI CEC pin.

  • Inter-Integrated Circuit (I²C) 1, open-drain clock line. Use an external pull-up. Bidirectional open drain #61 PB8
  • Inter-Integrated Circuit (I²C) 1, open-drain data line. Use an external pull-up. Bidirectional open drain #62 PB9
  • Inter-Integrated Circuit (I²C) 1, System Management Bus (SMBus) alert line. Open-drain SMBus alert #57 PB5
SPI1 · 2 mappings

Default

AFIO_MAPR.SPI1_REMAP = 0

  • Serial Peripheral Interface (SPI) 1, negative slave select (chip select), input in slave mode or input/output in master mode. Input or output, depending on mode #20 PA4
  • Serial Peripheral Interface (SPI) 1, serial clock, output in master mode or input in slave mode. Output in master mode, input in slave mode #21 PA5
  • Serial Peripheral Interface (SPI) 1, master in, slave out: data from slave to master. Input in master mode, output in slave mode #22 PA6
  • Serial Peripheral Interface (SPI) 1, master out, slave in: data from master to slave. Output in master mode, input in slave mode #23 PA7

↪ Remap

AFIO_MAPR.SPI1_REMAP = 1

Set AFIO_MAPR.SWJ_CFG = 010 to release JTAG pins and retain SWD. Disable asynchronous trace when using PB3.

  • Serial Peripheral Interface (SPI) 1, negative slave select (chip select), input in slave mode or input/output in master mode. Input or output, depending on mode #50 PA15
  • Serial Peripheral Interface (SPI) 1, serial clock, output in master mode or input in slave mode. Output in master mode, input in slave mode #55 PB3
  • Serial Peripheral Interface (SPI) 1, master in, slave out: data from slave to master. Input in master mode, output in slave mode #56 PB4
  • Serial Peripheral Interface (SPI) 1, master out, slave in: data from master to slave. Output in master mode, input in slave mode #57 PB5
TIM1 · 2 mappings

Default

AFIO_MAPR.TIM1_REMAP = 00

  • Timer 1, external trigger input. Input #45 PA12
  • Timer 1, channel 1 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #41 PA8
  • Timer 1, channel 2 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #42 PA9
  • Timer 1, channel 3 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #43 PA10
  • Timer 1, channel 4 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #44 PA11
  • Timer 1, break input for shutting off timer outputs. Input #33 PB12
  • Timer 1, channel 1 complementary pulse-width modulation (PWM) output. Output #34 PB13
  • Timer 1, channel 2 complementary pulse-width modulation (PWM) output. Output #35 PB14
  • Timer 1, channel 3 complementary pulse-width modulation (PWM) output. Output #36 PB15

↪ Partial remap

AFIO_MAPR.TIM1_REMAP = 01

  • Timer 1, external trigger input. Input #45 PA12
  • Timer 1, channel 1 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #41 PA8
  • Timer 1, channel 2 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #42 PA9
  • Timer 1, channel 3 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #43 PA10
  • Timer 1, channel 4 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #44 PA11
  • Timer 1, break input for shutting off timer outputs. Input #22 PA6
  • Timer 1, channel 1 complementary pulse-width modulation (PWM) output. Output #23 PA7
  • Timer 1, channel 2 complementary pulse-width modulation (PWM) output. Output #26 PB0
  • Timer 1, channel 3 complementary pulse-width modulation (PWM) output. Output #27 PB1
TIM2 · 4 mappings

Default

AFIO_MAPR.TIM2_REMAP = 00

  • Timer 2, channel 1 input capture, output compare or pulse-width modulation (PWM), or external trigger input. Channel I/O or trigger input #14 PA0
  • Timer 2, channel 2 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #15 PA1
  • Timer 2, channel 3 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #16 PA2
  • Timer 2, channel 4 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #17 PA3

↪ Partial remap 1

AFIO_MAPR.TIM2_REMAP = 01

Set AFIO_MAPR.SWJ_CFG = 010 to release JTAG pins and retain SWD. Disable asynchronous trace when using PB3.

  • Timer 2, channel 1 input capture, output compare or pulse-width modulation (PWM), or external trigger input. Channel I/O or trigger input #50 PA15
  • Timer 2, channel 2 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #55 PB3
  • Timer 2, channel 3 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #16 PA2
  • Timer 2, channel 4 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #17 PA3

↪ Partial remap 2

AFIO_MAPR.TIM2_REMAP = 10

  • Timer 2, channel 1 input capture, output compare or pulse-width modulation (PWM), or external trigger input. Channel I/O or trigger input #14 PA0
  • Timer 2, channel 2 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #15 PA1
  • Timer 2, channel 3 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #29 PB10
  • Timer 2, channel 4 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #30 PB11

↪ Full remap

AFIO_MAPR.TIM2_REMAP = 11

Set AFIO_MAPR.SWJ_CFG = 010 to release JTAG pins and retain SWD. Disable asynchronous trace when using PB3.

  • Timer 2, channel 1 input capture, output compare or pulse-width modulation (PWM), or external trigger input. Channel I/O or trigger input #50 PA15
  • Timer 2, channel 2 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #55 PB3
  • Timer 2, channel 3 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #29 PB10
  • Timer 2, channel 4 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #30 PB11
TIM3 · 3 mappings

Default

AFIO_MAPR.TIM3_REMAP = 00

  • Timer 3, channel 1 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #22 PA6
  • Timer 3, channel 2 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #23 PA7
  • Timer 3, channel 3 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #26 PB0
  • Timer 3, channel 4 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #27 PB1
  • Timer 3, external trigger input. Input #54 PD2

↪ Partial remap

AFIO_MAPR.TIM3_REMAP = 10

Set AFIO_MAPR.SWJ_CFG = 010 to release JTAG pins and retain SWD. Disable asynchronous trace when using PB3.

  • Timer 3, channel 1 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #56 PB4
  • Timer 3, channel 2 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #57 PB5
  • Timer 3, channel 3 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #26 PB0
  • Timer 3, channel 4 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #27 PB1
  • Timer 3, external trigger input. Input #54 PD2

↪ Full remap

AFIO_MAPR.TIM3_REMAP = 11

  • Timer 3, channel 1 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #37 PC6
  • Timer 3, channel 2 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #38 PC7
  • Timer 3, channel 3 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #39 PC8
  • Timer 3, channel 4 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #40 PC9
  • Timer 3, external trigger input. Input #54 PD2
TIM15 · 2 mappings

Default

AFIO_MAPR2.TIM15_REMAP = 0

  • Timer 15, channel 1 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #16 PA2
  • Timer 15, channel 2 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #17 PA3
  • Timer 15, channel 1 complementary pulse-width modulation (PWM) output. Output #36 PB15
  • Timer 15, break input for shutting off timer outputs. Input #42 PA9

↪ Remap

AFIO_MAPR2.TIM15_REMAP = 1

  • Timer 15, channel 1 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #35 PB14
  • Timer 15, channel 2 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #36 PB15
  • Timer 15, break input for shutting off timer outputs. Input #42 PA9
TIM16 · 2 mappings

Default

AFIO_MAPR2.TIM16_REMAP = 0

  • Timer 16, channel 1 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #61 PB8
  • Timer 16, channel 1 complementary pulse-width modulation (PWM) output. Output #58 PB6
  • Timer 16, break input for shutting off timer outputs. Input #57 PB5

↪ Remap

AFIO_MAPR2.TIM16_REMAP = 1

  • Timer 16, channel 1 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #22 PA6
  • Timer 16, channel 1 complementary pulse-width modulation (PWM) output. Output #58 PB6
  • Timer 16, break input for shutting off timer outputs. Input #57 PB5
TIM17 · 2 mappings

Default

AFIO_MAPR2.TIM17_REMAP = 0

  • Timer 17, channel 1 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #62 PB9
  • Timer 17, channel 1 complementary pulse-width modulation (PWM) output. Output #59 PB7
  • Timer 17, break input for shutting off timer outputs. Input #43 PA10

↪ Remap

AFIO_MAPR2.TIM17_REMAP = 1

  • Timer 17, channel 1 input capture, output compare or pulse-width modulation (PWM). Input or output, depending on channel mode #23 PA7
  • Timer 17, channel 1 complementary pulse-width modulation (PWM) output. Output #59 PB7
  • Timer 17, break input for shutting off timer outputs. Input #43 PA10
USART1 · 2 mappings

Default

AFIO_MAPR.USART1_REMAP = 0

  • Universal synchronous/asynchronous receiver/transmitter (USART) 1, transmit data output. Output #42 PA9
  • Universal synchronous/asynchronous receiver/transmitter (USART) 1, receive data input. Input #43 PA10
  • Universal synchronous/asynchronous receiver/transmitter (USART) 1, synchronous clock output. Output in synchronous mode #41 PA8
  • Universal synchronous/asynchronous receiver/transmitter (USART) 1, clear-to-send input. Input #44 PA11
  • Universal synchronous/asynchronous receiver/transmitter (USART) 1, request-to-send output. Output #45 PA12

↪ Remap

AFIO_MAPR.USART1_REMAP = 1

PB6 and PB7 share I²C1 functions.

  • Universal synchronous/asynchronous receiver/transmitter (USART) 1, transmit data output. Output #58 PB6
  • Universal synchronous/asynchronous receiver/transmitter (USART) 1, receive data input. Input #59 PB7
  • Universal synchronous/asynchronous receiver/transmitter (USART) 1, synchronous clock output. Output in synchronous mode #41 PA8
  • Universal synchronous/asynchronous receiver/transmitter (USART) 1, clear-to-send input. Input #44 PA11
  • Universal synchronous/asynchronous receiver/transmitter (USART) 1, request-to-send output. Output #45 PA12
USART2 · 1 mapping

Default

AFIO_MAPR.USART2_REMAP = 0

  • Universal synchronous/asynchronous receiver/transmitter (USART) 2, transmit data output. Output #16 PA2
  • Universal synchronous/asynchronous receiver/transmitter (USART) 2, receive data input. Input #17 PA3
  • Universal synchronous/asynchronous receiver/transmitter (USART) 2, synchronous clock output. Output in synchronous mode #20 PA4
  • Universal synchronous/asynchronous receiver/transmitter (USART) 2, clear-to-send input. Input #14 PA0
  • Universal synchronous/asynchronous receiver/transmitter (USART) 2, request-to-send output. Output #15 PA1

Device and package specifications

STM32F100R4 has 51 GPIO lines, 16 external ADC inputs, 1 SPI controllers, 1 I²C controllers, 2 USART controllers. The Cortex-M3 core runs at up to 24 MHz.

SPI2, I²C2, USART3 and TIM4 are absent on the 16 and 32 KiB devices.

For TFBGA64 (R4, R6, R8 and RB with 16, 32, 64 and 128 KiB Flash), see the ST ballout. For LQFP144 (ZC, ZD, ZE with 256, 384 and 512 KiB Flash), see the ST pinout.

Electrical reference tables

Electrical specifications for the pins and modes shown above. Source: ST DS6517 Rev 9 · PDF; RM0041 and AN2586 where noted.

Table 8 · Supply operating conditions

ParameterValue and conditions
VDD operating range2.0–3.6 VRelative to VSS. Connect every VDD and VSS pin.
VDDA operating range2.0–3.6 V · 2.4–3.6 V with ADCRelative to VSSA. Supply VDDA from the same source as VDD.
VBAT operating range1.8–3.6 VRelative to VSS. Connect to VDD when a separate backup supply is unused.
Back to selected pin ↑

Figure 10 · Main and analog supply bypass

ParameterValue and conditions
VDD bypass100 nFPlace one capacitor per VDD/VSS pair.
VDD bulk capacitor4.7 µFPlace at VDD_3.
VDDA bypass10 nF + 1 µFPlace close to VDDA/VSSA.
Ground reference0 VConnect all VSS and VSSA pins to system ground.
Back to selected pin ↑

AN2586 §2.2 · Backup supply bypass

ParameterValue and conditions
VBAT bypass100 nFAt VBAT when connected to VDD, as shown in the hardware guide. For a separate source check RM0041 §4.1.2 for startup current injection.
Back to selected pin ↑

Table 34 · Digital input levels and pull resistors

ParameterValue and conditions
Standard input LOW / HIGH≤1.16 V / ≥1.84 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
Standard input voltageVSS − 0.3 V to VDD + 0.3 VDigital mode, powered MCU. Stay within both current-injection and voltage ratings.
FT input LOW / HIGH≤1.16 V / ≥1.55 VAt VDD = 3.3 V, relative to VSS. Values rounded toward the guaranteed range.
FT digital input HIGHUp to 5.5 V (5.2 V at VDD = 2.0 V)Powered MCU. Disable internal pull-up and pull-down above VDD + 0.3 V.
Internal pull-up or pull-down30–50 kΩ (40 kΩ typical)Pull-up measured with VIN = VSS. Pull-down measured with VIN = VDD.
Back to selected pin ↑

Table 35 · Digital output levels

ParameterValue and conditions
Output LOW / HIGH≤0.4 V / ≥VDD − 0.4 VCMOS levels at 8 mA sink/source and 2.7 V < VDD < 3.6 V. Respect total supply and ground current limits.
Output LOW / HIGH at low supply≤0.4 V / ≥VDD − 0.4 VCharacterized at 6 mA sink/source and 2.0 V < VDD < 2.7 V.
Back to selected pin ↑

Table 4, note 5 · Backup-domain GPIO limits

ParameterValue and conditions
Backup-domain GPIO output2 MHz max · 30 pF maxPC13–PC15 share a 3 mA power switch. Keep these pins from sourcing load current.
Back to selected pin ↑

Table 42 · ADC conversion range

ParameterValue and conditions
ADC conversion inputVSSA to VDDA12-bit analog mode. VREF− must be at VSSA; on this package the reference pins are bonded to VSSA and VDDA.
Back to selected pin ↑

Table 43 · ADC sample time and source resistance

ParameterValue and conditions
ADC source resistance at 12 MHz≤0.4 kΩ at 1.5 cycles · ≤11.4 kΩ at 13.5 cyclesMaximum values for the corresponding sample time. Choose the sample time for the total driving impedance.
Back to selected pin ↑

Table 6 · Absolute maximum supply and ground currents

ParameterValue and conditions
Absolute maximum supply / ground current150 mA eachSum over all VDD/VDDA or VSS pins, including MCU and I/O load. Use the output-level specifications to design the working load.
Back to selected pin ↑

Table 37 · Reset thresholds

ParameterValue and conditions
Reset input LOW / HIGH≤0.8 V / ≥2.0 VRelative to VSS. An internal weak pull-up keeps NRST high when released.
Back to selected pin ↑

RM0041 §2.4 · Boot selection

ParameterValue and conditions
Boot selection0 → Flash · 1 → System memory or SRAMWith BOOT0 = 1, BOOT1 = 0 selects system memory and BOOT1 = 1 selects SRAM.
Back to selected pin ↑

Table 21 · High-speed external crystal oscillator

ParameterValue and conditions
HSE crystal frequency4–24 MHzCrystal mode. Use oscillator limits and the chosen crystal load parameters.
Back to selected pin ↑

Table 22 · Low-speed external crystal oscillator

ParameterValue and conditions
LSE crystal frequency32.768 kHzCrystal mode. Use the LSE oscillator conditions and the crystal’s load specification.
Back to selected pin ↑

ST documentation

Source register (JSON)