Spark Logic

STM32F103

STM32F103C8T6 LQFP48 · 7 × 7 mm

STM32F103RBT6

LQFP64 · 10 × 10 mm
Datasheet for STM32F103

Pinout

LQFP64 · TOP VIEW

Chip pinout. For power, look up VDD, VDDA or VBAT. VIN and VOUT are board labels; VIN in the datasheet means input voltage.

Pin colors
Find interface
Selected #1 VBAT Pin details below ↓

Details for the selected pin

#1 VBAT

Supply input

Backup power for the RTC, low-speed oscillator and backup registers.

Backup supply
1.8–3.6 V
Without a backup supply
Connect VBAT to VDD

Electrical reference tables

Pin list

64 / 64

Select a pin for wiring details. Hover, focus or tap an underlined signal to read its meaning.

PinPurposeVoltage summarySignals
Supply inputBackup power for the RTC, low-speed oscillator and backup registers.
Backup supply
1.8–3.6 V
 —
GPIO / tamper inputPort C bit 13. Tamper input for the RTC backup domain.
Digital input range
−0.3 V to VDD + 0.3 VStandard I/O
Real-time clock (RTC) tamper detection input.
GPIO / oscillator inputPort C bit 14. Input for the 32.768 kHz LSE crystal or external RTC clock.
External clock LOW
VSS to 0.3 × VDD
External clock HIGH
0.7 × VDD to VDD
Low-speed external (LSE) oscillator input for a 32.768 kHz crystal or external clock.
GPIO / oscillator outputPort C bit 15. LSE crystal amplifier output. Leave open in external clock bypass mode.
LSE mode
Crystal amplifier output
Low-speed external (LSE) crystal oscillator output.
Oscillator input / GPIOInput for the HSE crystal or external clock. Use PD01_REMAP = 1 for PD0 when HSE is unused.
External clock LOW
VSS to 0.3 × VDD
External clock HIGH
0.7 × VDD to VDD
Remapped Port D bit 0 when HSE is unused.
Oscillator output / GPIOHSE crystal amplifier output. Leave open in external clock bypass mode. Use PD01_REMAP = 1 for PD1 when HSE is unused.
HSE mode
Crystal amplifier output
Remapped Port D bit 1 when HSE is unused.
Reset I/OActive-low reset with an internal pull-up. Pull low to reset the chip.
Reset input LOW
≤ 0.8 V
Reset input HIGH
≥ 2.0 V
 —
GPIO / ADC inputPort C bit 0. Configurable digital input or output.
Digital input range
−0.3 V to VDD + 0.3 VStandard I/O
ADC input range
VSSA to VDDA0–3.3 V at VDDA = 3.3 V. Analog mode, 12-bit ADC.
Analog-to-digital converter (ADC) 1 or 2, analog input channel 10.
GPIO / ADC inputPort C bit 1. Configurable digital input or output.
Digital input range
−0.3 V to VDD + 0.3 VStandard I/O
ADC input range
VSSA to VDDA0–3.3 V at VDDA = 3.3 V. Analog mode, 12-bit ADC.
Analog-to-digital converter (ADC) 1 or 2, analog input channel 11.
GPIO / ADC inputPort C bit 2. Configurable digital input or output.
Digital input range
−0.3 V to VDD + 0.3 VStandard I/O
ADC input range
VSSA to VDDA0–3.3 V at VDDA = 3.3 V. Analog mode, 12-bit ADC.
Analog-to-digital converter (ADC) 1 or 2, analog input channel 12.
GPIO / ADC inputPort C bit 3. Configurable digital input or output.
Digital input range
−0.3 V to VDD + 0.3 VStandard I/O
ADC input range
VSSA to VDDA0–3.3 V at VDDA = 3.3 V. Analog mode, 12-bit ADC.
Analog-to-digital converter (ADC) 1 or 2, analog input channel 13.
GroundAnalog ground and internal negative ADC reference for these packages.
Ground reference
0 VConnect to system ground.
 —
Supply inputAnalog supply and internal positive ADC reference for these packages.
Analog supply
2.0–3.6 VADC off. Use the same supply source as VDD.
Analog supply
2.4–3.6 VADC enabled. Use the same supply source as VDD.
 —
GPIO / ADC inputPort A bit 0. Wake-up input for Standby mode. Also available as ADC channel 0, USART2 CTS or TIM2 channel 1 / external trigger.
Digital input range
−0.3 V to VDD + 0.3 VStandard I/O
ADC input range
VSSA to VDDA0–3.3 V at VDDA = 3.3 V. Analog mode, 12-bit ADC.
Standby wake-up input. Universal synchronous/asynchronous receiver/transmitter (USART) 2, clear-to-send input. Analog-to-digital converter (ADC) 1 or 2, analog input channel 0. Timer 2, channel 1 input capture, output compare or pulse-width modulation (PWM), or external trigger input.
GPIO / ADC inputPort A bit 1. Configurable digital input or output.
Digital input range
−0.3 V to VDD + 0.3 VStandard I/O
ADC input range
VSSA to VDDA0–3.3 V at VDDA = 3.3 V. Analog mode, 12-bit ADC.
Universal synchronous/asynchronous receiver/transmitter (USART) 2, request-to-send output. Analog-to-digital converter (ADC) 1 or 2, analog input channel 1. Timer 2, channel 2 input capture, output compare or pulse-width modulation (PWM).
GPIO / ADC inputPort A bit 2. Configurable digital input or output.
Digital input range
−0.3 V to VDD + 0.3 VStandard I/O
ADC input range
VSSA to VDDA0–3.3 V at VDDA = 3.3 V. Analog mode, 12-bit ADC.
Universal synchronous/asynchronous receiver/transmitter (USART) 2, transmit data output. Analog-to-digital converter (ADC) 1 or 2, analog input channel 2. Timer 2, channel 3 input capture, output compare or pulse-width modulation (PWM).
GPIO / ADC inputPort A bit 3. Configurable digital input or output.
Digital input range
−0.3 V to VDD + 0.3 VStandard I/O
ADC input range
VSSA to VDDA0–3.3 V at VDDA = 3.3 V. Analog mode, 12-bit ADC.
Universal synchronous/asynchronous receiver/transmitter (USART) 2, receive data input. Analog-to-digital converter (ADC) 1 or 2, analog input channel 3. Timer 2, channel 4 input capture, output compare or pulse-width modulation (PWM).
GroundDigital ground return. Connect every VSS pin.
Ground reference
0 VConnect to system ground.
 —
Supply inputMain digital supply. Connect every VDD pin.
Digital supply
2.0–3.6 VRelative to VSS
 —
GPIO / ADC inputPort A bit 4. Configurable digital input or output.
Digital input range
−0.3 V to VDD + 0.3 VStandard I/O
ADC input range
VSSA to VDDA0–3.3 V at VDDA = 3.3 V. Analog mode, 12-bit ADC.
Serial Peripheral Interface (SPI) 1, negative slave select (chip select), input in slave mode or input/output in master mode. Universal synchronous/asynchronous receiver/transmitter (USART) 2, synchronous clock output. Analog-to-digital converter (ADC) 1 or 2, analog input channel 4.
GPIO / ADC inputPort A bit 5. Configurable digital input or output.
Digital input range
−0.3 V to VDD + 0.3 VStandard I/O
ADC input range
VSSA to VDDA0–3.3 V at VDDA = 3.3 V. Analog mode, 12-bit ADC.
Serial Peripheral Interface (SPI) 1, serial clock, output in master mode or input in slave mode. Analog-to-digital converter (ADC) 1 or 2, analog input channel 5.
GPIO / ADC inputPort A bit 6. Configurable digital input or output.
Digital input range
−0.3 V to VDD + 0.3 VStandard I/O
ADC input range
VSSA to VDDA0–3.3 V at VDDA = 3.3 V. Analog mode, 12-bit ADC.
Serial Peripheral Interface (SPI) 1, master in, slave out: data from slave to master. Analog-to-digital converter (ADC) 1 or 2, analog input channel 6. Timer 3, channel 1 input capture, output compare or pulse-width modulation (PWM).
Remapped Timer 1, break input for shutting off timer outputs.
GPIO / ADC inputPort A bit 7. Configurable digital input or output.
Digital input range
−0.3 V to VDD + 0.3 VStandard I/O
ADC input range
VSSA to VDDA0–3.3 V at VDDA = 3.3 V. Analog mode, 12-bit ADC.
Serial Peripheral Interface (SPI) 1, master out, slave in: data from master to slave. Analog-to-digital converter (ADC) 1 or 2, analog input channel 7. Timer 3, channel 2 input capture, output compare or pulse-width modulation (PWM).
Remapped Timer 1, channel 1 complementary pulse-width modulation (PWM) output.
GPIO / ADC inputPort C bit 4. Configurable digital input or output.
Digital input range
−0.3 V to VDD + 0.3 VStandard I/O
ADC input range
VSSA to VDDA0–3.3 V at VDDA = 3.3 V. Analog mode, 12-bit ADC.
Analog-to-digital converter (ADC) 1 or 2, analog input channel 14.
GPIO / ADC inputPort C bit 5. Configurable digital input or output.
Digital input range
−0.3 V to VDD + 0.3 VStandard I/O
ADC input range
VSSA to VDDA0–3.3 V at VDDA = 3.3 V. Analog mode, 12-bit ADC.
Analog-to-digital converter (ADC) 1 or 2, analog input channel 15.
GPIO / ADC inputPort B bit 0. Configurable digital input or output.
Digital input range
−0.3 V to VDD + 0.3 VStandard I/O
ADC input range
VSSA to VDDA0–3.3 V at VDDA = 3.3 V. Analog mode, 12-bit ADC.
Analog-to-digital converter (ADC) 1 or 2, analog input channel 8. Timer 3, channel 3 input capture, output compare or pulse-width modulation (PWM).
Remapped Timer 1, channel 2 complementary pulse-width modulation (PWM) output.
GPIO / ADC inputPort B bit 1. Configurable digital input or output.
Digital input range
−0.3 V to VDD + 0.3 VStandard I/O
ADC input range
VSSA to VDDA0–3.3 V at VDDA = 3.3 V. Analog mode, 12-bit ADC.
Analog-to-digital converter (ADC) 1 or 2, analog input channel 9. Timer 3, channel 4 input capture, output compare or pulse-width modulation (PWM).
Remapped Timer 1, channel 3 complementary pulse-width modulation (PWM) output.
GPIO / boot inputPort B bit 2. Acts as BOOT1 at reset when BOOT0 is high: low selects system memory, high selects SRAM.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
After reset Port B bit 2 / boot selection input 1. Sampled with BOOT0 to select the boot memory.
GPIOPort B bit 10. Configurable digital input or output.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
Inter-Integrated Circuit (I²C) 2, open-drain clock line. Use an external pull-up. Universal synchronous/asynchronous receiver/transmitter (USART) 3, transmit data output.
Remapped Timer 2, channel 3 input capture, output compare or pulse-width modulation (PWM).
GPIOPort B bit 11. Configurable digital input or output.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
Inter-Integrated Circuit (I²C) 2, open-drain data line. Use an external pull-up. Universal synchronous/asynchronous receiver/transmitter (USART) 3, receive data input.
Remapped Timer 2, channel 4 input capture, output compare or pulse-width modulation (PWM).
GroundDigital ground return. Connect every VSS pin.
Ground reference
0 VConnect to system ground.
 —
Supply inputMain digital supply. Connect every VDD pin.
Digital supply
2.0–3.6 VRelative to VSS
 —
GPIOPort B bit 12. Configurable digital input or output.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
Serial Peripheral Interface (SPI) 2, negative slave select (chip select), input in slave mode or input/output in master mode. Inter-Integrated Circuit (I²C) 2, System Management Bus (SMBus) alert line. Universal synchronous/asynchronous receiver/transmitter (USART) 3, synchronous clock output. Timer 1, break input for shutting off timer outputs.
GPIOPort B bit 13. Configurable digital input or output.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
Serial Peripheral Interface (SPI) 2, serial clock, output in master mode or input in slave mode. Universal synchronous/asynchronous receiver/transmitter (USART) 3, clear-to-send input. Timer 1, channel 1 complementary pulse-width modulation (PWM) output.
GPIOPort B bit 14. Configurable digital input or output.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
Serial Peripheral Interface (SPI) 2, master in, slave out: data from slave to master. Universal synchronous/asynchronous receiver/transmitter (USART) 3, request-to-send output. Timer 1, channel 2 complementary pulse-width modulation (PWM) output.
GPIOPort B bit 15. Configurable digital input or output.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
Serial Peripheral Interface (SPI) 2, master out, slave in: data from master to slave. Timer 1, channel 3 complementary pulse-width modulation (PWM) output.
GPIOPort C bit 6. Configurable digital input or output.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
Remapped Timer 3, channel 1 input capture, output compare or pulse-width modulation (PWM).
GPIOPort C bit 7. Configurable digital input or output.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
Remapped Timer 3, channel 2 input capture, output compare or pulse-width modulation (PWM).
GPIOPort C bit 8. Configurable digital input or output.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
Remapped Timer 3, channel 3 input capture, output compare or pulse-width modulation (PWM).
GPIOPort C bit 9. Configurable digital input or output.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
Remapped Timer 3, channel 4 input capture, output compare or pulse-width modulation (PWM).
GPIOPort A bit 8. Configurable digital input or output.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
Universal synchronous/asynchronous receiver/transmitter (USART) 1, synchronous clock output. Timer 1, channel 1 input capture, output compare or pulse-width modulation (PWM). Microcontroller clock output.
GPIOPort A bit 9. Configurable digital input or output.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
Universal synchronous/asynchronous receiver/transmitter (USART) 1, transmit data output. Timer 1, channel 2 input capture, output compare or pulse-width modulation (PWM).
GPIOPort A bit 10. Configurable digital input or output.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
Universal synchronous/asynchronous receiver/transmitter (USART) 1, receive data input. Timer 1, channel 3 input capture, output compare or pulse-width modulation (PWM).
GPIO / USB D−Port A bit 11. USB Full Speed D−, CAN receive, USART1 CTS or TIM1 channel 4.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
Universal synchronous/asynchronous receiver/transmitter (USART) 1, clear-to-send input. Controller Area Network (CAN) receive input. Connect to the receive-data output (RXD) of a CAN transceiver. Universal Serial Bus (USB), Full Speed negative data line (D−). Timer 1, channel 4 input capture, output compare or pulse-width modulation (PWM).
GPIO / USB D+Port A bit 12. USB Full Speed D+, CAN transmit, USART1 RTS or TIM1 external trigger.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
Universal synchronous/asynchronous receiver/transmitter (USART) 1, request-to-send output. Controller Area Network (CAN) transmit output. Connect to the transmit-data input (TXD) of a CAN transceiver. Universal Serial Bus (USB), Full Speed positive data line (D+). Pull up with 1.5 kΩ to 3.0–3.6 V. Timer 1, external trigger input.
GPIO / debug I/OSWD data (SWDIO) or JTAG mode select (JTMS) after reset. Can be released for GPIO.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
After reset Joint Test Action Group (JTAG) test mode select / Serial Wire Debug (SWD) bidirectional data line.
GroundDigital ground return. Connect every VSS pin.
Ground reference
0 VConnect to system ground.
 —
Supply inputMain digital supply. Connect every VDD pin.
Digital supply
2.0–3.6 VRelative to VSS
 —
GPIO / debug inputSWD clock (SWCLK) or JTAG clock (JTCK) after reset. Can be released for GPIO.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
After reset JTAG test clock / Serial Wire Debug (SWD) clock input.
GPIO / debug inputJTAG data input (JTDI) after reset. Can be released for GPIO, SPI1 chip select or TIM2 channel 1 / external trigger.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
After reset JTAG test data input.
Remapped Timer 2, channel 1 input capture, output compare or pulse-width modulation (PWM), or external trigger input. Serial Peripheral Interface (SPI) 1, negative slave select (chip select), input in slave mode or input/output in master mode.
GPIOPort C bit 10. Configurable digital input or output.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
Remapped Universal synchronous/asynchronous receiver/transmitter (USART) 3, transmit data output.
GPIOPort C bit 11. Configurable digital input or output.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
Remapped Universal synchronous/asynchronous receiver/transmitter (USART) 3, receive data input.
GPIOPort C bit 12. Configurable digital input or output.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
Remapped Universal synchronous/asynchronous receiver/transmitter (USART) 3, synchronous clock output.
GPIOPort D bit 2. Configurable digital input or output.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
Timer 3, external trigger input.
GPIO / debug outputJTAG data output (JTDO) or trace output (TRACESWO). Can also carry SPI1 clock or TIM2 channel 2.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
After reset JTAG test data output / Serial Wire Output (SWO) trace data output.
Remapped Timer 2, channel 2 input capture, output compare or pulse-width modulation (PWM). Serial Peripheral Interface (SPI) 1, serial clock, output in master mode or input in slave mode.
GPIO / debug inputJTAG reset (JNTRST) after reset. Can also carry SPI1 MISO or TIM3 channel 1.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
After reset JTAG test reset input, active low.
Remapped Timer 3, channel 1 input capture, output compare or pulse-width modulation (PWM). Serial Peripheral Interface (SPI) 1, master in, slave out: data from slave to master.
GPIOPort B bit 5. Configurable digital input or output.
Digital input range
−0.3 V to VDD + 0.3 VStandard I/O
Inter-Integrated Circuit (I²C) 1, System Management Bus (SMBus) alert line.
Remapped Timer 3, channel 2 input capture, output compare or pulse-width modulation (PWM). Serial Peripheral Interface (SPI) 1, master out, slave in: data from master to slave.
GPIOPort B bit 6. Configurable digital input or output.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
Inter-Integrated Circuit (I²C) 1, open-drain clock line. Use an external pull-up. Timer 4, channel 1 input capture, output compare or pulse-width modulation (PWM).
Remapped Universal synchronous/asynchronous receiver/transmitter (USART) 1, transmit data output.
GPIOPort B bit 7. Configurable digital input or output.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
Inter-Integrated Circuit (I²C) 1, open-drain data line. Use an external pull-up. Timer 4, channel 2 input capture, output compare or pulse-width modulation (PWM).
Remapped Universal synchronous/asynchronous receiver/transmitter (USART) 1, receive data input.
Boot inputSampled at reset. Low selects user Flash. High selects system memory or SRAM according to BOOT1.
BOOT0 input range
0–5.5 V
 —
GPIOPort B bit 8. Configurable digital input or output.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
Timer 4, channel 3 input capture, output compare or pulse-width modulation (PWM).
Remapped Inter-Integrated Circuit (I²C) 1, open-drain clock line. Use an external pull-up. Controller Area Network (CAN) receive input. Connect to the receive-data output (RXD) of a CAN transceiver.
GPIOPort B bit 9. Configurable digital input or output.
Digital input range
−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range
−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
Timer 4, channel 4 input capture, output compare or pulse-width modulation (PWM).
Remapped Inter-Integrated Circuit (I²C) 1, open-drain data line. Use an external pull-up. Controller Area Network (CAN) transmit output. Connect to the transmit-data input (TXD) of a CAN transceiver.
GroundDigital ground return. Connect every VSS pin.
Ground reference
0 VConnect to system ground.
 —
Supply inputMain digital supply. Connect every VDD pin.
Digital supply
2.0–3.6 VRelative to VSS
 —

Compare variants

Cortex-M3Arm core
72 MHzMaximum core frequency
20 KBSRAM on both variants
2.0–3.6 VVDD operating voltage
LQFP48 / 7 × 7 mm

STM32F103C8T6

Flash
64 KB
I/O lines
37
ADC channels
10
View pinout ↑
LQFP64 / 10 × 10 mm

STM32F103RBT6

Flash
128 KB
I/O lines
51
ADC channels
16
View pinout ↑

The family supports USB Full Speed, CAN 2.0B, up to three USARTs, two SPI interfaces, and two I²C interfaces. See the pinout for signals available on each package.

Electrical reference tables

Electrical specifications for the pins and modes shown above. Source: ST DS5319 Rev 19.

Table 5 · PC13–PC15 output limits

ParameterValue and conditions
PC13–PC15 output speed≤ 2 MHzLoad capacitance ≤ 30 pF
PC13–PC15 output current≤ 3 mA sinkingDo not use as a current source.
Back to selected pin ↑

Table 9 · Supply and input voltage ranges

ParameterValue and conditions
Backup supply1.8–3.6 V
Digital input range−0.3 V to VDD + 0.3 VStandard I/O
Analog supply2.0–3.6 VADC off. Use the same supply source as VDD.
Digital supply2.0–3.6 VRelative to VSS
Digital input range−0.3 to 5.5 V5 V-tolerant I/O at 2.0 V < VDD ≤ 3.6 V
Digital input range−0.3 to 5.2 V5 V-tolerant I/O at VDD = 2.0 V
BOOT0 input range0–5.5 V
Back to selected pin ↑

Table 20 · HSE bypass clock

ParameterValue and conditions
External clock LOWVSS to 0.3 × VDD
External clock HIGH0.7 × VDD to VDD
HSE bypass clock frequency1–25 MHz
Back to selected pin ↑

Table 21 · LSE bypass clock

ParameterValue and conditions
External clock LOWVSS to 0.3 × VDD
External clock HIGH0.7 × VDD to VDD
Back to selected pin ↑

Table 36 · Digital input thresholds and internal pulls

ParameterValue and conditions
Input LOW≤ 0.35 × VDD≤ 1.155 V at VDD = 3.3 V
Input HIGH≥ 0.65 × VDD≥ 2.145 V at VDD = 3.3 V
Internal pull-up or pull-down30–50 kΩ
Internal pulls above VDD + 0.3 VDisable both pull-up and pull-down
Back to selected pin ↑

Table 37 · GPIO output levels

ParameterValue and conditions
Push-pull output LOW≤ 0.4 VWhen remapped to PD1 · At VDD = 3.3 V and 8 mA load
Push-pull output HIGH≥ 2.9 VWhen remapped to PD1 · At VDD = 3.3 V and 8 mA load
Push-pull output LOW≤ 0.4 VAt VDD = 3.3 V and 8 mA load
Push-pull output HIGH≥ 2.9 VAt VDD = 3.3 V and 8 mA load
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Table 39 · Reset input

ParameterValue and conditions
Reset input LOW≤ 0.8 V
Reset input HIGH≥ 2.0 V
Internal reset pull-up30–50 kΩ
Low pulse that passes the reset filter≥ 300 ns
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Table 45 · USB Full Speed supply

ParameterValue and conditions
USB Full Speed supply3.0–3.6 VVDD in USB mode. Use USB data-line signal levels.
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Table 47 · ADC input range

ParameterValue and conditions
ADC input rangeVSSA to VDDA0–3.3 V at VDDA = 3.3 V. Analog mode, 12-bit ADC.
Analog supply2.4–3.6 VADC enabled. Use the same supply source as VDD.
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Figure 14 · Supply decoupling

ParameterValue and conditions
Bypass capacitors10 nF and 1 µFBetween VDDA and VSSA
Digital supply decoupling100 nF at each VDD pin
Bulk capacitor4.7 µF at VDD_3
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Figure 31 · Reset capacitor

ParameterValue and conditions
Reset capacitor100 nFBetween NRST and ground
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