Spark Logic

uP9509P / uP9509S connection guide

uP9509P / uP9509S (VQFN-24) connection guide. Controller power and ground. One integrated phase.

VQFN-24

25 contacts Current package

uPI Semiconductor · 4 × 4 mm · 24 edge contacts and exposed ground pad

Controller power and ground

Required

Apply a regulated 5 V bias supply to PVCC and solder the exposed GND pad to the ground plane. VIN is the separate feed for the MOSFET power stage.

Place ceramic capacitors close to PVCC and VREF. Keep EN low during initial bias checks and follow the board’s power sequence.

Controller power and grounduP9509PVCCVREFGND (EP)5 V bias2 V outC1 ≥1 µFC2 ≥1 µF
  • PVCC · 5 V
    • 5 V bias rail
    • C1.1
  • Controller ground
    • Bias supply return
    • C1.2
    • C2.2
  • VREF · 2 V output
    • C2.1

Bench checks

  • Check continuity from the exposed pad to board ground before applying power.
  • Measure PVCC at the controller. Its operating range is 4.5–5.5 V and its rising reset threshold is typically 4.1 V.

uPI uP9509-DS-C3000 (December 2015) · pp. 2–5

Connection scenarios

One integrated phase

For a one-phase limit, pull ISEN2 up to PVCC through 100 kΩ. Use the board schematic to verify all other unused-stage connections.

Use the phase 1 gate, bootstrap and sense connections below.

One integrated phaseIntegrated phase 1uP9509Stage 1UGATE1LGATE1BOOT1PHASE1ISEN1Gate HGate LSWCB1RS1Phase selection at power-onISEN2RSEL 100 kΩPVCC
  • BOOT1
    • CB1.1
  • PHASE1
    • CB1.2
    • MOSFET switch node 1
    • Sense resistor 1.1
    • Inductor 1 input
  • High-side gate 1
    • High-side MOSFET gate 1
  • Low-side gate 1
    • Low-side MOSFET gate 1
  • Current sense 1
    • Sense resistor 1.2
  • PVCC · 5 V
    • RSEL.1
  • One-phase select
    • RSEL.2

Bench checks

  • Set the straps with power removed. The phase limit is sampled at PVCC power-on reset.
  • Verify the phase 1 bootstrap capacitor returns to PHASE1. Use the board’s documented sense resistor and MOSFETs.

uPI uP9509-DS-C3000 (December 2015) · pp. 2–5

VQFN-24 wiring map

External wiring example · One integrated phase

Highlighted contacts are used in the required step or selected circuit. Select a contact to highlight its wiring nets.

VQFN-24

5 · VID · Bottom side, contact 5 from the left

Marking-side view as drawn in the pin configuration. Pin 1 is at the left end of the bottom edge.
Selected pin details

5 · VID

Input · Control

PWMVID from the GPU. The buffer can detect a high-impedance input during boot.

uPI uP9509-DS-C3000 (December 2015) · p. 3

Electrical limits · Pin in the reference

Models and documents

The two order codes use the same contact positions. The reference opens with P specifications. Select S to see its VIN range, phase straps and third-stage sense resistor. PGF860 is part of the supplied chip marking. The ordering table identifies the device by uP9509P.

uP9509PQAG
uP9509P top mark · 4.5–26 V VIN.
uP9509SQAG
uP9509S top mark · 3–26 V VIN.