Spark Logic

uP9509P / uP9509S connection guide

uP9509P / uP9509S (VQFN-24) connection guide. Controller power and ground. One integrated phase.

VQFN-24

25 contacts Current package

uPI Semiconductor · 4 × 4 mm · 24 edge contacts and exposed ground pad

Controller power and ground

Required

Apply a regulated 5 V bias supply to PVCC and solder the exposed GND pad to the ground plane. VIN is the separate feed for the MOSFET power stage.

Place ceramic capacitors close to PVCC and VREF. Keep EN low during initial bias checks and follow the board’s power sequence.

Controller power and grounduP9509PVCCVREFGND (EP)5 V bias2 V outC1 ≥1 µFC2 ≥1 µF
  • PVCC · 5 V
    • 5 V bias rail
    • C1.1
  • Controller ground
    • Bias supply return
    • C1.2
    • C2.2
  • VREF · 2 V output
    • C2.1

Bench checks

  • Check continuity from the exposed pad to board ground before applying power.
  • Measure PVCC at the controller. Its operating range is 4.5–5.5 V and its rising reset threshold is typically 4.1 V.

uPI uP9509-DS-C3000 (December 2015) · pp. 2–5

Connection scenarios

PWMVID, feedback and power good

Route GPU PWMVID to VID and connect REFADJ, VREF and REFIN through the board’s reference filter and bias network. The component values set boot and operating voltage.

Route FB and FBRTN to the load-side sense network, retain the COMP network and pull PGOOD up to the receiver rail.

PWMVID, feedback and power gooduP9509VIDGPU PWMVIDREFADJVREFREFINReference RCFBFBRTNLoad senseCOMPCompensationPGOODReceiverwith pull-up
  • GPU PWMVID
    • →
    • GPU PWMVID output
  • Filtered reference input
    • Reference network output
  • Reference filter drive
    • Reference network PWM input
  • Reference bias
    • Reference network bias
  • Remote positive sense
    • Positive sense network
  • Remote return
    • GPU sense return
  • Loop compensation
    • Compensation network
  • Power good
    • Receiver input
    • Pull-up resistor

Bench checks

  • With the board schematic, verify the boot reference before relying on PWM duty cycle to set the output voltage.
  • Check VOUT and PGOOD during startup. Use a differential measurement across UGATEx and PHASEx to inspect high-side drive.

uPI uP9509-DS-C3000 (December 2015) · pp. 2–5

VQFN-24 wiring map

External wiring example · PWMVID, feedback and power good

Highlighted contacts are used in the required step or selected circuit. Select a contact to highlight its wiring nets.

VQFN-24

6 · REFADJ · Bottom side, contact 6 from the left

Marking-side view as drawn in the pin configuration. Pin 1 is at the left end of the bottom edge.
Selected pin details

6 · REFADJ

Buffered PWM · Outputs

Feeds the external PWMVID filter. It becomes high impedance during boot; the board’s network then establishes REFIN.

uPI uP9509-DS-C3000 (December 2015) · p. 3

Connected nets

Electrical limits · Pin in the reference

Models and documents

The two order codes use the same contact positions. The reference opens with P specifications. Select S to see its VIN range, phase straps and third-stage sense resistor. PGF860 is part of the supplied chip marking. The ordering table identifies the device by uP9509P.

uP9509PQAG
uP9509P top mark · 4.5–26 V VIN.
uP9509SQAG
uP9509S top mark · 3–26 V VIN.