Spark Logic

uP9509P / uP9509S pinout

Synchronous buck controllers for GPU power. The VQFN-24 package integrates two MOSFET gate drivers and can control a third phase with an external driver.

VQFN-24

25 contacts Current package

uPI Semiconductor · 4 × 4 mm · 24 edge contacts and exposed ground pad

uP9509S top mark · 3–26 V VIN.

VQFN-24 pinout

VQFN-24

12 · COMP · Right side, contact 1 from the top

Marking-side view as drawn in the pin configuration. Pin 1 is at the left end of the bottom edge.
Selected pin details

12 · COMP

Error amplifier output · Outputs

Connect the compensation network sized for the board’s output filter and load.

uPI uP9509S-DS-F0000 (July 2018) · p. 5

Electrical limits · Link to this pin

PWMVID, feedback and power good

Open this wiring example

Controller power and ground

Controller power and grounduP9509PVCCVREFGND (EP)5 V bias2 V outC1 ≥1 µFC2 ≥1 µF
  • PVCC · 5 V
    • 5 V bias rail
    • C1.1
  • Controller ground
    • Bias supply return
    • C1.2
    • C2.2
  • VREF · 2 V output
    • C2.1

Connection guide

All 25 pins

PinSignalDirectionFunction
1BOOT1 Bootstrap supplyBootstrap supply Place the phase 1 bootstrap capacitor between BOOT1 and PHASE1.
2UGATE1 Gate driveGate drive Drives the high-side MOSFET gate. Its reference is PHASE1.
3EN InputInput Active-high enable. Check the board’s power sequence before driving EN.
4PSI InputInput GPU power-saving input. Its voltage selects the phase and conduction mode within the power-on configuration. Drive PSI to a defined level. Do not leave it open.
5VID InputInput PWMVID from the GPU. The buffer can detect a high-impedance input during boot.
6REFADJ Buffered PWMBuffered PWM Feeds the external PWMVID filter. It becomes high impedance during boot; the board’s network then establishes REFIN.
7REFIN Analog referenceAnalog reference Reference for the control loop. The external network sets this voltage, including the startup target.
8VREF Reference outputReference output Nominal 2 V reference output. Place at least 1 µF from VREF to GND.
9TON Timing inputTiming input Connect to power-stage VIN through the board’s on-time resistor. Do not add a capacitor to TON.
10FBRTN Remote sense returnRemote sense return Route to the GPU load-side ground sense point. Keep the separate sense route away from switching nodes.
11FB Analog feedbackAnalog feedback Inverting error amplifier input. Connect to the load-side sense network specified for the board.
12COMP Error amplifier outputError amplifier output Connect the compensation network sized for the board’s output filter and load.
13ISEN3 Current senseCurrent sense Senses the external third stage through the specified resistor from PHASE3. Use 510 Ω with the third stage installed. Leave ISEN3 open for one or two phases.
14ISEN2 Current sense / strapCurrent sense / strap Senses PHASE2 through a resistor in normal operation. A 100 kΩ pull-up to PVCC selects a one-phase limit at power-on reset.
15ISEN1 Current senseCurrent sense Senses PHASE1 through a resistor for current balance and protection.
16PGOOD Open drainOpen drain Pull up to the board’s receiver logic rail through a resistor.
17UGATE2 Gate driveGate drive Drives the phase 2 high-side MOSFET gate, referenced to PHASE2.
18BOOT2 Bootstrap supplyBootstrap supply Place the phase 2 bootstrap capacitor between BOOT2 and PHASE2.
19PHASE2 Switch-node referenceSwitch-node reference Connect to the phase 2 switch node and the return of its bootstrap capacitor.
20LGATE2 Gate driveGate drive Drives the phase 2 low-side MOSFET gate.
21PVCC Controller supplyController supply Supply 4.5–5.5 V, with at least 1 µF of ceramic bypass capacitance to GND.
22PWM3 PWM output / strapPWM output / strap Controls the external phase 3 driver, or serves as a power-on configuration strap. Ground PWM3 directly for one or two phases. Leave ISEN3 open in those modes.
23LGATE1 Gate driveGate drive Drives the phase 1 low-side MOSFET gate.
24PHASE1 Switch-node referenceSwitch-node reference Connect to the phase 1 switch node and the return of its bootstrap capacitor.
EPGND Exposed padExposed pad Solder the exposed pad to a low-impedance ground plane. It is the controller ground.

Signal assignments

External phase 3

PWM3 drives the external driver. ISEN3 senses that stage’s switch node through a resistor.

Electrical limits

ParameterLimitConditions and source
PVCC controller supply4.5–5.5 V4.5–5.5 V Nominal 5 V bias. The MOSFET rail has a separate VIN range. uPI uP9509S-DS-F0000 (July 2018) · pp. 11–13
Power-stage VIN3–26 V3–26 V Recommended operating range. Use the board’s component and supply ratings for the assembled regulator. uPI uP9509S-DS-F0000 (July 2018) · pp. 11–13
PVCC rising reset threshold3.9–4.3 V3.9–4.3 V Typical 4.1 V. This threshold is below the normal operating range. uPI uP9509S-DS-F0000 (July 2018) · pp. 11–13
EN and VID logicLOW ≤ 0.6 V · HIGH ≥ 1.2 VLOW ≤ 0.6 V · HIGH ≥ 1.2 V The typical application uses 1.8 V PWMVID. uPI uP9509S-DS-F0000 (July 2018) · pp. 11–13
VREF1.98–2.02 V1.98–2.02 V Electrical characteristics at PVCC = 5 V and TA = 25 °C. Bypass with at least 1 µF. uPI uP9509S-DS-F0000 (July 2018) · pp. 11–13
External REFIN0.2–2.0 V0.2–2.0 V Reference-input range. The required GPU rail voltage is set by the board design. uPI uP9509S-DS-F0000 (July 2018) · pp. 11–13
Phase 3 sense resistor510 Ω510 Ω Between the external PHASE3 switch node and ISEN3. uPI uP9509S-DS-F0000 (July 2018) · p. 5

Models and documents

The two order codes use the same contact positions. The reference opens with P specifications. Select S to see its VIN range, phase straps and third-stage sense resistor. PGF860 is part of the supplied chip marking. The ordering table identifies the device by uP9509P.

uP9509PQAG
uP9509P top mark · 4.5–26 V VIN.
uP9509SQAG
uP9509S top mark · 3–26 V VIN.