I²C bus
Use 7-bit address 0x50 for a single part. The chip ignores the three low address bits and also responds to 0x51–0x57.
Send the full memory address as the next byte.
24C02 EEPROM (24LC02B) pinout
The 24LC02B is a 2-Kbit I²C EEPROM that stores 256 B and writes up to 8 bytes per page.
SC-70-5 pinout
SC-70-5
1 · SCL
Serial clock from the host. On an open-drain bus, provide a pull-up to the bus rail.
All 5 pins
| Pin | Signal | Direction | Function |
|---|---|---|---|
| 1 | SCL Input | Input | Serial clock from the host. On an open-drain bus, provide a pull-up to the bus rail. |
| 2 | VSS Reference | Reference | Supply return and signal reference. Connect to the host ground. |
| 3 | SDA Open-drain I/O | Open-drain I/O | Serial address and data. Pull up to the bus rail and let the host and EEPROM drive only LOW. |
| 4 | VCC Supply | Supply | Regulated 2.5–5.5 V supply. Bypass locally to VSS. |
| 5 | WP Input | Input | Tie to VCC to protect the entire array or to VSS to enable writes. Reads are available in both states. |
Signal assignments
Write protection
Tie to VCC to protect the entire array or to VSS to enable writes. Reads are available in both states.
Electrical limits
| Parameter | Limit | Conditions and source |
|---|---|---|
| Operating supply2.5–5.5 V | 2.5–5.5 V | Industrial (I) and extended (E) temperature ranges are listed in the device selection table. Check the exact order code. DS20001709P · p. 1 |
| I²C clock limit400 kHz | 400 kHz | Meet the AC timing, voltage and pull-up requirements. The wiring example uses 100 kHz. DS20001709P · §1, Table 1-2 |
| Input thresholdsLOW ≤ 0.3 × VCC · HIGH ≥ 0.7 × VCC | LOW ≤ 0.3 × VCC · HIGH ≥ 0.7 × VCC | Relative to VSS over the specified supply range. Use a common-voltage bus or level shifting. DS20001709P · §1, Table 1-1 |
| SDA output LOW≤ 0.40 V | ≤ 0.40 V | Tested at 3.0 mA sink current and VCC = 2.5 V. DS20001709P · §1, Table 1-1 |
| Memory and word address256 B · 1 address byte | 256 B · 1 address byte | Offsets 0x0000–0x00FF. Client and memory addressing are described in the I²C signal assignment. DS20001709P · p. 1 and §5 |
| Page write8 bytes · 5 ms maximum write cycle | 8 bytes · 5 ms maximum write cycle | Split writes at page boundaries and use acknowledge polling after STOP. Read explicitly addressed data after power-up. DS20001709P · Table 1-2 and §§6–8 |
Models and documents
This reference covers the standard package codes listed for Microchip 24LC02B in the linked datasheet. Match the full manufacturer part number before wiring a device marked 24C02. Use its own datasheet for other manufacturers or the Microchip AA and FC versions. Microchip 24C02C requires 4.5–5.5 V and uses A0–A2 as address inputs. Its WP input protects offsets 0x80–0xFF.
- 24LC02B
- The /LT package suffix selects this outline. Check the ordering table for supported temperature and reel combinations.
- Microchip 24LC02B datasheet· DS20001709P · 2025-09 · Device selection and diagrams on p. 1, electrical limits in §1, pin assignments in §2 and transactions in §§5–8.
- Microchip AN1028 · Recommended usage of I²C serial EEPROMs· DS01028B · Figure 1, bus pull-ups, power-up, acknowledge polling and recovery.
- Microchip 24C02C datasheet· DS20001202K · See p. 1 and §2 for the 5 V supply, address straps and upper-half write protection.
- Microchip DFN-8 package drawing· C04-123 and C04-2123 Rev E · MC outline and optional center land pad.
- Source versions and checksums· Document revisions, source URLs and SHA-256 checksums for the consulted manufacturer files.