Spark Logic

24C08 EEPROM (24LC08B) pinout

The 24LC08B is a 8-Kbit I²C EEPROM that stores 1 KiB and writes up to 16 bytes per page.

PDIP-8 8 contacts
SOIC-8 8 contacts
MSOP-8 8 contacts
TSSOP-8 8 contacts
DFN-8 9 contacts

TDFN-8

9 contacts Current package
SOT-23-5 5 contacts

Microchip Technology · 2 × 3 × 0.8 mm leadless body · 0.50 mm pitch · Microchip package code /MNY

TDFN-8 pinout

Top view · Locate pin 1 using the package index mark.
EP is the exposed center pad on the underside.
Selected pin details

7 · WP

Input · Control

Tie to VCC to protect the entire array or to VSS to enable writes. Reads are available in both states.

DS20001710M · §2 and Table 2-1

Electrical limits · Link to this pin

All 9 pins

PinSignalDirectionFunction
1A0 UnconnectedUnconnected No internal connection. Leave open. The address selection is handled in the I²C control byte.
2A1 UnconnectedUnconnected No internal connection. Leave open. The address selection is handled in the I²C control byte.
3A2 UnconnectedUnconnected No internal connection. Leave open. The address selection is handled in the I²C control byte.
4VSS ReferenceReference Supply return and signal reference. Connect to the host ground.
5SDA Open-drain I/OOpen-drain I/O Serial address and data. Pull up to the bus rail and let the host and EEPROM drive only LOW.
6SCL InputInput Serial clock from the host. On an open-drain bus, provide a pull-up to the bus rail.
7WP InputInput Tie to VCC to protect the entire array or to VSS to enable writes. Reads are available in both states.
8VCC SupplySupply Regulated 2.5–5.5 V supply. Bypass locally to VSS.
EPExposed pad Optional referenceOptional reference The underside exposed pad can be tied to VSS or left electrically floating. The numbered VSS terminal remains the supply return.

Signal assignments

I²C bus

Use 7-bit address 0x50 + (offset >> 8), then send the low byte of the offset.

B1:B0 select one of four 256-byte blocks. The chip ignores the next higher address bit, so 0x54–0x57 mirror 0x50–0x53.

Write protection

Tie to VCC to protect the entire array or to VSS to enable writes. Reads are available in both states.

Electrical limits

ParameterLimitConditions and source
Operating supply2.5–5.5 V2.5–5.5 V Industrial (I) and extended (E) temperature ranges are listed in the device selection table. Check the exact order code. DS20001710M · p. 1
I²C clock limit400 kHz400 kHz Meet the AC timing, voltage and pull-up requirements. The wiring example uses 100 kHz. DS20001710M · §1, Table 1-2
Input thresholdsLOW ≤ 0.3 × VCC · HIGH ≥ 0.7 × VCCLOW ≤ 0.3 × VCC · HIGH ≥ 0.7 × VCC Relative to VSS over the specified supply range. Use a common-voltage bus or level shifting. DS20001710M · §1, Table 1-1
SDA output LOW≤ 0.40 V≤ 0.40 V Tested at 3.0 mA sink current and VCC = 2.5 V. DS20001710M · §1, Table 1-1
Memory and word address1 KiB · 1 address byte1 KiB · 1 address byte Offsets 0x0000–0x03FF. Client and memory addressing are described in the I²C signal assignment. DS20001710M · p. 1 and §5
Page write16 bytes · 5 ms maximum write cycle16 bytes · 5 ms maximum write cycle Split writes at page boundaries and use acknowledge polling after STOP. Read explicitly addressed data after power-up. DS20001710M · Table 1-2 and §§6–8

Models and documents

This reference covers the standard package codes listed for Microchip 24LC08B in the linked datasheet. Match the full manufacturer part number before wiring a device marked 24C08. Use its own datasheet for other manufacturers or the Microchip AA and FC versions. The four-ball CSP drawing in the family datasheet applies to 24AA08.

24LC08B
The /MNY package suffix selects this outline. Check the ordering table for supported temperature and reel combinations.