Spark Logic

24C32 EEPROM (24LC32A) pinout

The 24LC32A is a 32-Kbit I²C EEPROM that stores 4 KiB and writes up to 32 bytes per page.

PDIP-8 8 contacts
SOIC-8 8 contacts
SOIJ-8 8 contacts
MSOP-8 8 contacts
TSSOP-8 8 contacts
X-rotated TSSOP-8 8 contacts
DFN-8 9 contacts

TDFN-8

9 contacts Current package
SOT-23-5 5 contacts

Microchip Technology · 2 × 3 × 0.8 mm leadless body · 0.50 mm pitch · Microchip package code /MNY

TDFN-8 pinout

Top view · Locate pin 1 using the package index mark.
EP is the exposed center pad on the underside.
Selected pin details

6 · SCL

Input · Clock inputs / oscillator

Serial clock from the host. On an open-drain bus, provide a pull-up to the bus rail.

DS20001713P · §2 and Table 2-1

Electrical limits · Link to this pin

All 9 pins

PinSignalDirectionFunction
1A0 InputInput Chip select bit 0. Strap to VSS for 0 or to VCC for 1.
2A1 InputInput Chip select bit 1. Strap to VSS for 0 or to VCC for 1.
3A2 InputInput Chip select bit 2. Strap to VSS for 0 or to VCC for 1.
4VSS ReferenceReference Supply return and signal reference. Connect to the host ground.
5SDA Open-drain I/OOpen-drain I/O Serial address and data. Pull up to the bus rail and let the host and EEPROM drive only LOW.
6SCL InputInput Serial clock from the host. On an open-drain bus, provide a pull-up to the bus rail.
7WP InputInput Tie to VCC to protect the entire array or to VSS to enable writes. Reads are available in both states.
8VCC SupplySupply Regulated 2.5–5.5 V supply. Bypass locally to VSS.
EPExposed pad Optional referenceOptional reference The underside exposed pad can be tied to VSS or left electrically floating. The numbered VSS terminal remains the supply return.

Signal assignments

I²C bus

The 7-bit client address is 0x50 + 4×A2 + 2×A1 + A0. Strap each pin to VSS or VCC before power-up.

Send two memory-address bytes, high byte first. The usable offset ends at 0x0FFF.

Client address straps

Strap the three inputs before operating the part. Each distinct combination selects one client address. Up to eight individually addressed parts can share a bus.

Write protection

Tie to VCC to protect the entire array or to VSS to enable writes. Reads are available in both states.

Electrical limits

ParameterLimitConditions and source
Operating supply2.5–5.5 V2.5–5.5 V Industrial (I) and extended (E) temperature ranges are listed in the device selection table. Check the exact order code. DS20001713P · p. 1
I²C clock limit400 kHz400 kHz Meet the AC timing, voltage and pull-up requirements. The wiring example uses 100 kHz. DS20001713P · §1, Table 1-2
Input thresholdsLOW ≤ 0.3 × VCC · HIGH ≥ 0.7 × VCCLOW ≤ 0.3 × VCC · HIGH ≥ 0.7 × VCC Relative to VSS over the specified supply range. Use a common-voltage bus or level shifting. DS20001713P · §1, Table 1-1
SDA output LOW≤ 0.40 V≤ 0.40 V Specified at 2.1 mA sink current with VCC = 2.5 V and at 3.0 mA with VCC = 4.5 V. DS20001713P · §1, Table 1-1
Memory and word address4 KiB · 2 address bytes4 KiB · 2 address bytes Offsets 0x0000–0x0FFF. Client and memory addressing are described in the I²C signal assignment. DS20001713P · p. 1 and §5
Page write32 bytes · 5 ms maximum write cycle32 bytes · 5 ms maximum write cycle Split writes at page boundaries and use acknowledge polling after STOP. Read explicitly addressed data after power-up. DS20001713P · Table 1-2 and §§6–8

Models and documents

This reference covers the standard package codes listed for Microchip 24LC32A and the 24LC32AX pin assignment in the linked datasheet. Match the full manufacturer part number before wiring a device marked 24C32. Use its own datasheet for other manufacturers or the Microchip AA and FC versions.

24LC32A
The /MNY package suffix selects this outline. Check the ordering table for supported temperature and reel combinations.