Spark Logic

24C512 EEPROM (24LC512) pinout

The 24LC512 is a 512-Kbit I²C EEPROM that stores 64 KiB and writes up to 128 bytes per page.

PDIP-8 8 contacts
SOIC-8 8 contacts
SOIJ-8 8 contacts
TSSOP-8 8 contacts

TSSOP-14

14 contacts Current package
DFN-S-8 9 contacts

Microchip Technology · 14 leads · 0.65 mm lead pitch · Microchip package code /ST14

TSSOP-14 pinout

Top view · Locate pin 1 using the package index mark.
Selected pin details

8 · SDA

Open-drain I/O · Bidirectional

Serial address and data. Pull up to the bus rail and let the host and EEPROM drive only LOW.

DS20001754R · §2 and Table 2-1

Electrical limits · Link to this pin

All 14 pins

PinSignalDirectionFunction
1A0 InputInput Chip select bit 0. Strap to VSS for 0 or to VCC for 1.
2A1 InputInput Chip select bit 1. Strap to VSS for 0 or to VCC for 1.
3NC UnconnectedUnconnected No internal connection. Leave open.
4NC UnconnectedUnconnected No internal connection. Leave open.
5NC UnconnectedUnconnected No internal connection. Leave open.
6A2 InputInput Chip select bit 2. Strap to VSS for 0 or to VCC for 1.
7VSS ReferenceReference Supply return and signal reference. Connect to the host ground.
8SDA Open-drain I/OOpen-drain I/O Serial address and data. Pull up to the bus rail and let the host and EEPROM drive only LOW.
9SCL InputInput Serial clock from the host. On an open-drain bus, provide a pull-up to the bus rail.
10NC UnconnectedUnconnected No internal connection. Leave open.
11NC UnconnectedUnconnected No internal connection. Leave open.
12NC UnconnectedUnconnected No internal connection. Leave open.
13WP InputInput Tie to VCC to protect the entire array or to VSS to enable writes. Reads are available in both states.
14VCC SupplySupply Regulated 2.5–5.5 V supply. Bypass locally to VSS.

Signal assignments

I²C bus

The 7-bit client address is 0x50 + 4×A2 + 2×A1 + A0. Strap each pin to VSS or VCC before power-up.

Send two memory-address bytes, high byte first. The usable offset ends at 0xFFFF.

Client address straps

Strap the three inputs before operating the part. Each distinct combination selects one client address. Up to eight individually addressed parts can share a bus.

Write protection

Tie to VCC to protect the entire array or to VSS to enable writes. Reads are available in both states.

Electrical limits

ParameterLimitConditions and source
Operating supply2.5–5.5 V2.5–5.5 V Industrial (I) and extended (E) temperature ranges are listed in the device selection table. Check the exact order code. DS20001754R · p. 1
I²C clock limit400 kHz400 kHz Meet the AC timing, voltage and pull-up requirements. The wiring example uses 100 kHz. DS20001754R · §1, Table 1-2
Input thresholdsLOW ≤ 0.3 × VCC · HIGH ≥ 0.7 × VCCLOW ≤ 0.3 × VCC · HIGH ≥ 0.7 × VCC Relative to VSS over the specified supply range. Use a common-voltage bus or level shifting. DS20001754R · §1, Table 1-1
SDA output LOW≤ 0.40 V≤ 0.40 V Specified at 2.1 mA sink current with VCC = 2.5 V and at 3.0 mA with VCC = 4.5 V. DS20001754R · §1, Table 1-1
Memory and word address64 KiB · 2 address bytes64 KiB · 2 address bytes Offsets 0x0000–0xFFFF. Client and memory addressing are described in the I²C signal assignment. DS20001754R · p. 1 and §5
Page write128 bytes · 5 ms maximum write cycle128 bytes · 5 ms maximum write cycle Split writes at page boundaries and use acknowledge polling after STOP. Read explicitly addressed data after power-up. DS20001754R · Table 1-2 and §§6–8

Models and documents

This reference covers the standard package codes listed for Microchip 24LC512 in the linked datasheet. Match the full manufacturer part number before wiring a device marked 24C512. Use its own datasheet for other manufacturers or the Microchip AA and FC versions. The eight-ball CSP is listed for 24AA512. The five-lead SOT-23 and 8-lead UDFN are listed for 24FC512.

24LC512
The /ST14 package suffix selects this outline. Check the ordering table for supported temperature and reel combinations.