I²C bus
The 7-bit client address is 0x50 + 4×A2 + 2×A1 + A0. Strap each pin to VSS or VCC before power-up.
Send two memory-address bytes, high byte first. The usable offset ends at 0x1FFF.
24C64 EEPROM (24LC64) pinout
The 24LC64 is a 64-Kbit I²C EEPROM that stores 8 KiB and writes up to 32 bytes per page.
MSOP-8 pinout
5 · SDA
Serial address and data. Pull up to the bus rail and let the host and EEPROM drive only LOW.
All 8 pins
| Pin | Signal | Direction | Function |
|---|---|---|---|
| 1 | A0 Input | Input | Chip select bit 0. Strap to VSS for 0 or to VCC for 1. |
| 2 | A1 Input | Input | Chip select bit 1. Strap to VSS for 0 or to VCC for 1. |
| 3 | A2 Input | Input | Chip select bit 2. Strap to VSS for 0 or to VCC for 1. |
| 4 | VSS Reference | Reference | Supply return and signal reference. Connect to the host ground. |
| 5 | SDA Open-drain I/O | Open-drain I/O | Serial address and data. Pull up to the bus rail and let the host and EEPROM drive only LOW. |
| 6 | SCL Input | Input | Serial clock from the host. On an open-drain bus, provide a pull-up to the bus rail. |
| 7 | WP Input | Input | Tie to VCC to protect the entire array or to VSS to enable writes. Reads are available in both states. |
| 8 | VCC Supply | Supply | Regulated 2.5–5.5 V supply. Bypass locally to VSS. |
Signal assignments
Client address straps
Strap the three inputs before operating the part. Each distinct combination selects one client address. Up to eight individually addressed parts can share a bus.
Write protection
Tie to VCC to protect the entire array or to VSS to enable writes. Reads are available in both states.
Electrical limits
| Parameter | Limit | Conditions and source |
|---|---|---|
| Operating supply2.5–5.5 V | 2.5–5.5 V | Industrial (I) and extended (E) temperature ranges are listed in the device selection table. Check the exact order code. DS20001189V · p. 1 |
| I²C clock limit400 kHz | 400 kHz | Meet the AC timing, voltage and pull-up requirements. The wiring example uses 100 kHz. DS20001189V · §1, Table 1-2 |
| Input thresholdsLOW ≤ 0.3 × VCC · HIGH ≥ 0.7 × VCC | LOW ≤ 0.3 × VCC · HIGH ≥ 0.7 × VCC | Relative to VSS over the specified supply range. Use a common-voltage bus or level shifting. DS20001189V · §1, Table 1-1 |
| SDA output LOW≤ 0.40 V | ≤ 0.40 V | Specified at 2.1 mA sink current with VCC = 2.5 V and at 3.0 mA with VCC = 4.5 V. DS20001189V · §1, Table 1-1 |
| Memory and word address8 KiB · 2 address bytes | 8 KiB · 2 address bytes | Offsets 0x0000–0x1FFF. Client and memory addressing are described in the I²C signal assignment. DS20001189V · p. 1 and §5 |
| Page write32 bytes · 5 ms maximum write cycle | 32 bytes · 5 ms maximum write cycle | Split writes at page boundaries and use acknowledge polling after STOP. Read explicitly addressed data after power-up. DS20001189V · Table 1-2 and §§6–8 |
Models and documents
This reference covers the standard package codes listed for Microchip 24LC64 and the 24LC64X pin assignment in the linked datasheet. Match the full manufacturer part number before wiring a device marked 24C64. Use its own datasheet for other manufacturers or the Microchip AA and FC versions. The five-ball Chip Scale package is an industrial 24AA64 option, and the DFN-S package is listed for 24FC64.
- 24LC64
- The /MS package suffix selects this outline. Check the ordering table for supported temperature and reel combinations.
- Microchip 24LC64 datasheet· DS20001189V · 2025-01 · Device selection and diagrams on p. 1, electrical limits in §1, pin assignments in §2 and transactions in §§5–8.
- Microchip AN1028 · Recommended usage of I²C serial EEPROMs· DS01028B · Figure 1, bus pull-ups, power-up, acknowledge polling and recovery.
- Microchip DFN-8 package drawing· C04-123 and C04-2123 Rev E · MC outline and optional center land pad.
- Source versions and checksums· Document revisions, source URLs and SHA-256 checksums for the consulted manufacturer files.