Spark Logic

74AHCT595D connection guide

Wiring for one register or a two-register cascade.

SO16 (D)

9.90 × 3.90 mm · 1.27 mm pitch
SOT109-1 package outline

Connect and bypass the supply

With power off, wire regulated 5 V to 16 VCC and connect 8 GND to the controller ground. Fit one 100 nF ceramic capacitor per IC close to these pins. Use a capacitor rated above the supply (for example, 16 V). Repeat the circuit for each chip.

5 V to pin 16, ground to pin 8 and 100 nF across both pins+5 VGND100 nF16 VCC8 GND

After wiring the logic and before sending clocks, measure VCC relative to pin 8. Expect 4.5–5.5 V. Keep host outputs LOW or high impedance while the register supply is off.

1 Q1 2 Q2 3 Q3 4 Q4 5 Q5 6 Q6 7 Q7 8 GND Used in this circuit
16 VCC Used in this circuit15 Q0 14 DS 13 OE 12 STCP 11 SHCP 10 MR 9 Q7S
Top view · Pin 1 at upper left · Schematic outline

Wire the data and clocks

Use three push-pull controller signals for data and clocks, with a common ground. A 3.3 V controller can drive the AHCT inputs if its guaranteed LOW is ≤ 0.8 V and HIGH is ≥ 2.0 V, and the input transitions meet the 20 ns/V limit. The parallel outputs and Q7S are 5 V-domain signals. Use a 5 V-tolerant receiver or level translation.

+5 V connects A 10 MR. Host data connects A 14 DS. Host shift connects A 11 SHCP. Host latch connects A 12 STCP+5 VA·10 MRHost dataA·14 DSHost shiftA·11 SHCPHost latchA·12 STCP

Leave A pin 9 open. The host drives DS, SHCP and STCP independently.

Register A

1 Q1 2 Q2 3 Q3 4 Q4 5 Q5 6 Q6 7 Q7 Used in this circuit8 GND Used in this circuit
16 VCC Used in this circuit15 Q0 14 DS Used in this circuit13 OE Used in this circuit12 STCP Used in this circuit11 SHCP Used in this circuit10 MR Used in this circuit9 Q7S
Top view · Pin 1 at upper left · Schematic outline

Keep the outputs off during startup

On each chip, pull 13 OE up to 5 V with 10 kΩ. Use a push-pull driver powered from the same 5 V rail for OE. Let the resistor hold OE HIGH while the driver is high impedance at startup. Drive HIGH before the test and drive LOW only after latching known data. Keep this node away from 3.3 V pins without 5 V tolerance. Tie MR HIGH. The initial shift and storage words are undefined. With OE HIGH, Q0–Q7 are high impedance. Add receiver-side bias if a defined load state is required.

If the controller pins float during reset, add a 10 kΩ pulldown to ground on DS, STCP and each SHCP line. Check the host’s HIGH level with that load.

10 kΩ pull-up and 5 V push-pull driver at OE pin 13. Repeat per chip.+5 V10 kΩPin 13 OE5 V push-pull driver

Shift, latch and verify

  1. Keep OE HIGH on each chip. Start with SHCP and STCP LOW, and keep STCP LOW while shifting.
  2. Send 0x80, most significant bit (MSB) first, with 8 rising edges per shift-clock line. At a 1 MHz bench clock, set DS early in the LOW half-cycle and keep it stable until the clock returns LOW.
  3. After the final SHCP rising edge, wait at least 1 µs in this bench test, then pulse STCP HIGH for at least 1 µs. Drive OE LOW only after the latch pulse.
  4. Use a high-impedance probe rated for the 5 V signals and referenced to GND. Expect HIGH at A · 7 Q7 and LOW on the other parallel outputs. Leave unused outputs open. Send a new word with STCP LOW to check that the old word stays visible until STCP rises.

For a shifted pattern, check the bit order and count SHCP edges. For a stale pattern, check STCP and OE. In the cascade, the first byte ends in B and the second in A. See AHCT timing limits.

Ordering and documents

Nexperia lists the active order code below (12NC 935265559118). Package marking is 74AHCT595D.

  • 74AHCT595D,118

SO16 pin map: § 6.1 (D package) and Table 2. Function and waveforms: Table 3 and Figures 6–11. Mechanical outline: Figure 12.