Spark Logic

74HC04 connection guide

Wire and test the TI SN74HC04 as an inverter or buffer.

Connect and bypass the supply

With power off, connect a regulated 4.5 V supply to 14 VCC and its return to 7 GND. Fit a 100 nF ceramic capacitor directly across these pins with short leads. Connect the logic source and meter grounds to the same return.

4.5 V to pin 14, return to pin 7 and 100 nF across both pins4.5 VReturn100 nF14 VCC7 GND

Finish the logic wiring below before powering up. Verify 4.5 V at pin 14 with the meter common at pin 7.

1 1A 2 1Y 3 2A 4 2Y 5 3A 6 3Y 7 GND Used in this circuit
14 VCC Used in this circuit13 6A 12 6Y 11 5A 10 5Y 9 4A 8 4Y
Top view · Pin 1 at upper left · Schematic outline

Choose the output polarity

Connect a fast CMOS source that swings from 0 V to VCC to 1A (pin 1). Read the result at 1Y (pin 2).

Inverter. Input pin 1, output pin 2. Unused inputs 3, 5, 9, 11, 13 connect to pin 7.IN → 1 1A2 1Y → OUT3 2A5 3A9 4A11 5A13 6A7 GND

Tie unused inputs 3, 5, 9, 11, 13 to GND and leave their outputs open. Apply the logic signal only while the IC is powered.

1 1A Used in this circuit2 1Y Used in this circuit3 2A Used in this circuit4 2Y 5 3A Used in this circuit6 3Y 7 GND Used in this circuit
14 VCC 13 6A Used in this circuit12 6Y 11 5A Used in this circuit10 5Y 9 4A Used in this circuit8 4Y
Top view · Pin 1 at upper left · Schematic outline
Arrows show signal direction between paired pins.

Check both logic states

Input (pin 1)Output (pin 2)
LOW (0 V)HIGH
HIGH (VCC)LOW

Measure the settled output relative to pin 7 with a high-impedance meter (for example, 10 MΩ). At 4.5 V and an output load of 20 µA or less, expect LOW ≤ 0.1 V and HIGH ≥ 4.4 V. If either state is wrong, verify the supply and input swing at the IC before checking the pin numbering and jumpers. See the electrical limits.

Package and documents

TI package code DB · 6.5 × 5.3 mm nominal body · 0.65 mm lead pitch. Use TI’s package outline for footprint dimensions and tolerances.

Order codes use the SN74HC04 prefix. Suffixes for this package in TI’s 23 October 2026 addendum: DBR, DBR.A, DBRE4, DBRG4 (last-time buy).

Circuit references: §§ 5, 6.3, 6.5, 8.3, 9 and 10.