74HC14 connection guide
Wire a TI SN74HC14 to invert a logic signal or convert a slow edge to a digital transition.
Connect and bypass the supply
With power off, connect a regulated 4.5 V supply to 14 VCC and its return to 7 GND. Fit C1, a 100 nF ceramic capacitor rated at least 16 V, directly across these pins with short leads. Connect the logic source and meter grounds to the same return.
Finish the logic wiring below before powering up. Verify 4.5 V at pin 14 with the meter common at pin 7.
Choose a signal circuit
Put R1 (10 kΩ) between a rail-to-rail source and 1A (pin 1). Connect C2 (100 nF) from pin 1 to 7 GND. The resistor and capacitor slow the input edge. The Schmitt input switches at separate rising and falling thresholds, as described in TI’s Schmitt-trigger brief. Read the result at 1Y (pin 2).
Tie unused inputs 3, 5, 9, 11, 13 to pin 7 and leave their outputs open. Keep the source within the IC’s rails and enable it only while the IC is powered.
Arrows show signal direction between paired pins.
Check both logic states
| Source voltage | Output (pin 2) |
|---|---|
| LOW (0 V) | HIGH |
| HIGH (VCC) | LOW |
Measure the settled output relative to pin 7 with a high-impedance meter. At 4.5 V and a load of 20 µA or less, expect LOW ≤ 0.1 V and HIGH ≥ 4.4 V. If either state is wrong, check pin 14, pin 1 and any jumper at the package before checking the output.
Verify edge shaping
Use a 0–4.5 V, 100 Hz square wave at 50% duty cycle. Set the generator for its actual high-impedance load and verify both levels. With both oscilloscope probes referenced to pin 7, compare the slow charge and discharge at pin 1 with the sharp transitions at pin 2. A 10× probe limits loading. If pulses disappear, check whether pin 1 reaches the switching thresholds before the source reverses.
Use a 1% resistor rated at least 0.1 W and a ±10% ceramic capacitor rated at least 16 V. R × C gives 1 ms nominal and about 0.89–1.11 ms from nominal part tolerances alone. The largest ideal initial resistor dissipation is 4.5² / 10,000 ≈ 2 mW. For a low-impedance source and nominal R and C, the datasheet thresholds put the rising crossing at about 0.42–1.19 ms and the falling crossing at about 0.61–1.61 ms after a rail-to-rail step. These are the times for the exponential rise or decay at pin 1 to reach the corresponding threshold. Account for source resistance, effective capacitance and threshold spread in timing-sensitive designs.
The RC network attenuates short disturbances. Longer pulses or noise large enough to cross both thresholds can still switch the output. For a mechanical switch, choose the time constant from measured bounce and verify both transitions.
Package and documents
TI package code D · 8.65 × 3.9 mm nominal body · 1.27 mm lead pitch. Use TI’s package outline for footprint dimensions and tolerances.
TI lists these active order codes in its 18 September 2026 addendum. SN74HC14DR, SN74HC14DR.A, SN74HC14DRG3, SN74HC14DRG3.A, SN74HC14DRG4, SN74HC14DRG4.A. Obsolete codes in the same package SN74HC14D, SN74HC14DT.
- TI D package drawing (PDF)
- TI SNx4HC14 datasheet (PDF)· SCLS085L, Rev. L (February 2025), with package option addendum
- TI SN74HC14 product and ordering information
- TI Understanding Schmitt Triggers· SCEA046B, Rev. B (April 2025). Slow edges, noise, hysteresis and switch filtering.
TI SCLS085L §§ 7.3 and 8 explain input behavior, clock polarity, bypassing and unused pins.