74HC245 bus transceiver

Pinout and operating limits for the Nexperia 74HC245, an eight-bit non-inverting CMOS transceiver.

Pinout

DHVQFN20 · Transparent top view · Pin 1 at upper left · Schematic outline
EP is the exposed center pad on the underside.
Arrows show signal direction between paired pins.

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20 · VCC

Positive supply· 2.0–6.0 V

Connect to the regulated supply and bypass locally to pin 10.

Electrical limits

20 terminals and exposed pad

Pin	Name	Role	Operating range
1	DIR	Direction input	0 V to VCC
2	A0	Port A data	0 V to VCC
3	A1	Port A data	0 V to VCC
4	A2	Port A data	0 V to VCC
5	A3	Port A data	0 V to VCC
6	A4	Port A data	0 V to VCC
7	A5	Port A data	0 V to VCC
8	A6	Port A data	0 V to VCC
9	A7	Port A data	0 V to VCC
10	GND	Ground reference	0 V
11	B7	Port B data	0 V to VCC
12	B6	Port B data	0 V to VCC
13	B5	Port B data	0 V to VCC
14	B4	Port B data	0 V to VCC
15	B3	Port B data	0 V to VCC
16	B2	Port B data	0 V to VCC
17	B1	Port B data	0 V to VCC
18	B0	Port B data	0 V to VCC
19	/OE	Active-low output enable	0 V to VCC
20	VCC	Positive supply	2.0–6.0 V
EP	Exposed pad	Optional underside pad	Float or GND

Direction and output enable

Result	/OE	DIR
A → B	LOW	HIGH
B → A	LOW	LOW
Both ports high impedance (Z)	HIGH	Either

/OE is active-low. When enabled, the receiving port reproduces the driving port’s logic without inversion. With /OE HIGH, Z means the output drivers release both buses. A released bus may float or take a level from an external driver or bias. There is no reset or direction detection. Define both controls and hold /OE HIGH during handoff.

Electrical limits

Recommended operation for Nexperia 74HC245 is VCC 2.0–6.0 V, ambient −40 to +125 °C, and input and output voltages from GND to VCC. All voltages are relative to pin 10. Each connected driver must meet CMOS thresholds on the shared voltage domain. Check the guaranteed levels in both directions for any interface using a different rail. The I/O clamp paths remain present in high impedance and can back-power an unpowered device.

CMOS input levels and edge limits

VCC	VIL max	VIH min	Max ns per volt
2.0 V	0.50 V	1.50 V	625 ns/V
4.5 V	1.35 V	3.15 V	139 ns/V
6.0 V	1.80 V	4.20 V	83 ns/V

Output levels at 4.5 V

Load magnitude	VOL max	VOH min
20 µA	0.10 V	4.40 V
6 mA	0.40 V	3.70 V

Output levels apply at valid input levels over −40 to +125 °C. High-impedance leakage is bounded by ±10 µA at 6.0 V over that temperature range with the datasheet test conditions. At 4.5 V and 50 pF, data propagation delay is 27 ns maximum and enable or disable delay is 45 ns maximum over the same temperature range.

Absolute maximum ratings include ±35 mA at a single output, 70 mA into VCC and 70 mA magnitude through GND. These are stress limits. Check package dissipation, aggregate current and guaranteed output levels when loading multiple bits.

Sources: datasheet §7 Table 4, §8 Table 5, §9 Table 6 and §10 Table 7.

Package and documents

74HC245BQ · Nexperia SOT764-1 · 4.5 × 2.5 mm body · 0.5 mm terminal pitch. Production order code 74HC245BQ,115.Catalog also lists 74HC245BQ/GX (in development).

Scope: Nexperia’s commercial 74HC245 packages in Rev. 9. The legacy N (PDIP20) and DB (SSOP20) were removed in earlier revisions. The shared datasheet also describes 74HCT245, which has different input thresholds and operating supply limits. The automotive 74HC245-Q100 series has its own datasheet.

The series catalog lists −40 to +85 °C for 74HC245BQ. Rev. 9 Table 1 lists −40 to +125 °C. Confirm the temperature rating of your order code with Nexperia if operating above +85 °C.

Nexperia 74HC245 datasheet (PDF)· 74HC_HCT245 Rev. 9 · 9 May 2025
SOT764-1 package drawing (PDF)
74HC245BQ product and order codes
Nexperia series and ordering status

Pin assignments and exposed pad: §5, p. 3. Package versions: §3 Table 1. Outline: §11 Fig. 8.