Spark Logic

74HC245 connection guide

Set up a one-bit test and use a high-impedance interval to hand the bus to the other driver.

Power the IC with its outputs disabled

With power off, wire a regulated 4.5 V rail to pin 20 VCC and the common return to pin 10 GND. Place one 100 nF ceramic capacitor (16 V or higher) close to the IC across those pins. Share the return with the controller and both endpoints. Use rail-compatible controls and endpoints on this same supply.

4.5 V to pin 20, common return to pin 10, and 100 nF directly across the supply pins.4.5 VCommon return100 nF20 VCC10 GND

Pull /OE (pin 19) up to VCC with 10 kΩ so it defaults HIGH while the powered controller output is high impedance. Use a push-pull control with fast edges for switching. The pull-up adds about 0.45 mA at LOW on this rail. Hold DIR at a defined level through startup, using a 10 kΩ pull-down if the DIR controller starts in high impedance. Keep external signals within the rails, including during power sequencing.

1 DIR 2 A0 3 A1 4 A2 5 A3 6 A4 7 A5 8 A6 9 A7 10 GND Used in this circuit
20 VCC Used in this circuit19 /OE 18 B0 17 B1 16 B2 15 B3 14 B4 13 B5 12 B6 11 B7
Top view · Pin 1 at upper left · Schematic outline

Wire and bias the data pins

Connect endpoint A to A0 (pin 2) and endpoint B to B0 (pin 18). Use endpoints that can switch between driving and a high-impedance input. The controller or bus protocol must coordinate both endpoint drivers and the 74HC245 controls. Connect the controller outputs to DIR (pin 1) and /OE (pin 19). Power up with both endpoints in receive mode and /OE HIGH.

Endpoint A to pin 2, endpoint B to pin 18. Controller to DIR pin 1 and /OE pin 19. A 10 kΩ resistor pulls /OE up to VCC. Bias each data pin individually as shown next.VCC10 kΩEndpoint AEndpoint B2 A018 B0A1–A7B1–B7Bias eachBias each1 DIRDIR control19 /OEOE control
For each bit 0 through 7, connect one 10 kΩ resistor from An to common ground and one from Bn to common ground.AnBn10 kΩ10 kΩ

Fit one 10 kΩ pull-down per data pin, A0–A7 (2–9) and B0–B7 (11–18), including the two connected to the endpoints. Each resistor loads a HIGH by about 0.45 mA at 4.5 V. The resistors define LOW when the drivers release, including during handoff. Sample only during a valid transfer and verify total loading and leakage with the endpoints attached.

Test the signal path

B → A

Start with /OE HIGH. Configure A as an input, set DIR LOW and establish valid data at B0. Then drive /OE LOW.

/OE LOW · DIR LOW

StateEndpoint AEndpoint B
B → AReceive Drive

Read the arrow from B0 (18) to A0 (2). Drive 0 V and then 4.5 V at the source. With total output load ≤ 6 mA, including the pull-down and endpoint, expect ≤ 0.40 V and then ≥ 3.70 V, respectively. Measure relative to pin 10 with a high-impedance meter.

1 DIR Used in this circuit2 A0 Used in this circuit3 A1 4 A2 5 A3 6 A4 7 A5 8 A6 9 A7 10 GND
20 VCC 19 /OE Used in this circuit18 B0 Used in this circuit17 B1 16 B2 15 B3 14 B4 13 B5 12 B6 11 B7
TSSOP20 · Top view · Pin 1 at upper left · Schematic outline
Arrows show signal direction between paired pins.

The map highlights the test bit and its controls. DIR and /OE apply to all eight bits.

Complete A → B to B → A handoff

Phase/OEDIREnd AEnd B
A drivesLOW HIGH Drive Receive
Release bothHIGH HIGH Receive Receive
Change DIRHIGH LOW Receive Receive
Prepare BHIGH LOW Receive Drive
B drivesLOW LOW Receive Drive
  1. Begin with endpoint A driving valid data and endpoint B configured as an input.
  2. Drive /OE HIGH and wait for the 74HC245 output to release. Then put endpoint A in receive mode and wait for its output to release. Endpoint B stays in receive mode.
  3. With both endpoint drivers off and /OE still HIGH, drive DIR LOW and let it settle at the IC pin.
  4. Keep /OE HIGH and endpoint A in receive mode. Enable endpoint B’s driver and wait for valid data at B0.
  5. Pull /OE LOW only after B0 is valid and A is receiving. Allow enable and data settling time before sampling A0. Swap the port roles for the return handoff.

At 4.5 V, 50 pF and −40 to +125 °C, the 74HC245 output enable and disable delays are each 45 ns maximum under the datasheet test conditions. Budget from the control signal reaching the pin. Include worst-case release and enable times of the external endpoints, board loading, DIR and data settling, and margin. Confirm the timing and direction at the pins with a scope before using the sequence at speed.

Source for logic and timing: datasheet §6 Table 3, §9 Table 6 and §10 Table 7 and Fig. 4.

Package and documents

74HC245PW · Nexperia SOT360-1 · 6.5 × 4.4 mm body · 0.65 mm terminal pitch. Production order code 74HC245PW,118.Catalog also lists 74HC245PW/G600J and 74HC245PW/GJ (in development).

Scope: Nexperia’s commercial 74HC245 packages in Rev. 9. The legacy N (PDIP20) and DB (SSOP20) were removed in earlier revisions. The shared datasheet also describes 74HCT245, which has different input thresholds and operating supply limits. The automotive 74HC245-Q100 series has its own datasheet.

Pin assignments and exposed pad: §5, p. 3. Package versions: §3 Table 1. Outline: §11 Fig. 7.