74HC4051 analog multiplexer
Package pinouts, channel addresses and operating limits for the Texas Instruments CD74HC4051.
Pinout
Lines show bidirectional switch paths.
1 A4
Bidirectional channel 4 · VEE to VCC
With pin 6 LOW and S2 S1 S0 = 100, this channel connects to COM.
All 16 pins
| Pin | Name | Role | Range |
|---|---|---|---|
| 1 | A4 | Bidirectional channel 4 | VEE to VCC |
| 2 | A6 | Bidirectional channel 6 | VEE to VCC |
| 3 | COM | Common terminal (A) | VEE to VCC |
| 4 | A7 | Bidirectional channel 7 | VEE to VCC |
| 5 | A5 | Bidirectional channel 5 | VEE to VCC |
| 6 | E | Active-low enable (INH) | 0 V to VCC |
| 7 | VEE | Lower analog rail | See supply limits |
| 8 | GND | Logic and supply reference | 0 V reference |
| 9 | S2 | Address bit 2 | 0 V to VCC |
| 10 | S1 | Address bit 1 | 0 V to VCC |
| 11 | S0 | Address bit 0 | 0 V to VCC |
| 12 | A3 | Bidirectional channel 3 | VEE to VCC |
| 13 | A0 | Bidirectional channel 0 | VEE to VCC |
| 14 | A1 | Bidirectional channel 1 | VEE to VCC |
| 15 | A2 | Bidirectional channel 2 | VEE to VCC |
| 16 | VCC | Positive supply | See supply limits |
Channel addresses
With E (INH, pin 6) LOW, read the binary address in S2 S1 S0 order (pins 9, 10, 11). S0 is the least significant bit. With E HIGH, every switch opens regardless of S2–S0.
| S2 S1 S0 | Closed path with E LOW |
|---|---|
| 000 | 13 A0 ↔ 3 COM |
| 001 | 14 A1 ↔ 3 COM |
| 010 | 15 A2 ↔ 3 COM |
| 011 | 12 A3 ↔ 3 COM |
| 100 | 1 A4 ↔ 3 COM |
| 101 | 5 A5 ↔ 3 COM |
| 110 | 2 A6 ↔ 3 COM |
| 111 | 4 A7 ↔ 3 COM |
Recommended operating limits
| Parameter | Recommended range |
|---|---|
| VCC relative to GND | 2 V to 6 V |
| VEE relative to GND | −6 V to 0 V |
| VCC − VEE | 2 V to 10 V |
| Analog I/O (COM and A0–A7) | VEE to VCC |
| Digital controls (E and S0–S2) | 0 V to VCC |
| Ambient temperature | −55 °C to +125 °C |
All three supply limits apply together. Tying VEE to GND gives a unipolar range of 0 V to VCC. For example, +4.5 V at VCC and −4.5 V at VEE allow signals from −4.5 V to +4.5 V while the controls remain referenced to GND.
HC digital input thresholds
| VCC | VIL max (LOW) | VIH min (HIGH) |
|---|---|---|
| 2 V | 0.5 V | 1.5 V |
| 4.5 V | 1.35 V | 3.15 V |
| 6 V | 1.8 V | 4.2 V |
Check the driver’s guaranteed HIGH and LOW levels. For a 3.3 V controller driving an HC part at 5 V, verify compatibility or use a level translator.
Switch resistance and settling
At VCC = 4.5 V, VEE = 0 V and 1 mA test current, the full-range ON resistance is 90 Ω typical and 180 Ω maximum at 25 °C (270 Ω maximum over −55 °C to +125 °C). It adds to source resistance. For an ADC, account for loading, leakage and acquisition time. Break-before-make opens the old switch first, so a high-impedance node can float between selections.
Source sections 5.4–5.5 and 7.4 of TI SCHS122O.
Package and documents
TI package code D · 9.9 × 3.9 mm nominal body · 1.27 mm lead pitch. Use the outline drawing for footprint dimensions and tolerances.
| Ordering code | Status in TI addendum, 7 Oct 2026 |
|---|---|
| CD74HC4051M96 | Active |
| CD74HC4051M96.A | Active |
| CD74HC4051M | Obsolete |
| CD74HC4051M96G3 | Obsolete |
| CD74HC4051M96G4 | Obsolete |
| CD74HC4051MT | Obsolete |
- TI CD74HC4051 datasheet (PDF)· SCHS122O, Rev. O, January 2026
- TI CD74HC4051 product and package information
- TI SOIC-16 outline (PDF)· MPDS178G
See pin assignments, switch truth table, operating limits and supply bypass guidance. This reference covers the TI catalog CD74HC4051.