74HC4053 triple analog switch
Pinouts and operating limits for the Texas Instruments CD74HC4053, a set of three independent bidirectional 2:1 switches with a shared inhibit input.
Pinout
Lines show bidirectional switch paths.
5 · C0
Group C throw selected when S2 is LOW · VEE to VCC
Signal flow is bidirectional through the selected switch. Keep the signal in range even when this path is open.
Switch terminals and controls
All 16 pins
| Pin | Name | Role | Range |
|---|---|---|---|
| 1 | B1 | Group B throw selected when S1 is HIGH | VEE to VCC |
| 2 | B0 | Group B throw selected when S1 is LOW | VEE to VCC |
| 3 | C1 | Group C throw selected when S2 is HIGH | VEE to VCC |
| 4 | COM C | Group C common terminal | VEE to VCC |
| 5 | C0 | Group C throw selected when S2 is LOW | VEE to VCC |
| 6 | EN | Active-low enable (E̅ in TI pinout, INH by function): LOW enables all groups; HIGH opens all paths | GND to VCC |
| 7 | VEE | Negative analog rail; tie to GND for single-supply operation | −6 to 0 V |
| 8 | GND | Logic and supply reference | 0 V |
| 9 | S2 | Group C select: LOW chooses C0; HIGH chooses C1 | GND to VCC |
| 10 | S1 | Group B select: LOW chooses B0; HIGH chooses B1 | GND to VCC |
| 11 | S0 | Group A select: LOW chooses A0; HIGH chooses A1 | GND to VCC |
| 12 | A0 | Group A throw selected when S0 is LOW | VEE to VCC |
| 13 | A1 | Group A throw selected when S0 is HIGH | VEE to VCC |
| 14 | COM A | Group A common terminal | VEE to VCC |
| 15 | COM B | Group B common terminal | VEE to VCC |
| 16 | VCC | Positive supply and upper analog rail | 2 to 6 V |
Switch groups
Drive EN (6) LOW to close one path in each group. Every group has its own select input. EN HIGH opens all paths regardless of select levels. The switches are break-before-make when changing throws. Set all four control pins to defined levels during startup.
| Group and select | LOW · throw 0 | HIGH · throw 1 |
|---|---|---|
| A · S0 (11) | 14 ↔ 12 | 14 ↔ 13 |
| B · S1 (10) | 15 ↔ 2 | 15 ↔ 1 |
| C · S2 (9) | 4 ↔ 5 | 4 ↔ 3 |
Pairs are shown as common pin ↔ throw pin. Test each path in the connection guide.
Electrical limits
Recommended operating conditions
| Parameter | Range |
|---|---|
| VCC · positive supply | 2 to 6 V |
| VEE · negative analog rail | −6 to 0 V |
| VCC − VEE · total rail span | 2 to 10 V |
| Analog terminals | VEE to VCC |
| Digital controls | GND to VCC |
| Ambient temperature | −55 to +125 °C |
Apply all three rail limits together. Voltages are relative to GND except the rail span. For example, VCC = +5 V and VEE = 0 V gives a 0 to +5 V analog range. With VCC = +4.5 V and VEE = −4.5 V, the analog range is −4.5 to +4.5 V and the digital inputs still swing from 0 to +4.5 V.
HC digital input thresholds
| VCC | VIL max (LOW) | VIH min (HIGH) |
|---|---|---|
| 2 V | 0.5 V | 1.5 V |
| 4.5 V | 1.35 V | 3.15 V |
| 6 V | 1.8 V | 4.2 V |
Check the driver's guaranteed LOW and HIGH output levels against the HC limits at your supply voltage. A 3.3 V GPIO driving a 5 V HC control input requires a level-compatibility check.
On-resistance and loading
At VCC = 4.5 V, VEE = 0 V, 25 °C and 1 mA, on-resistance across the analog signal range is 90 Ω typical and 180 Ω maximum. It rises to a 270 Ω maximum across −55 to +125 °C under the same supply and current conditions. Allow for voltage drop and RC settling when driving a load or sampling capacitor.
Source: TI SCHS122O, §§ 5.4–5.5 (pp. 7–10), § 7.3 and Table 7-3 (p. 25).
Package and documents
PW · 5 × 4.4 mm nominal body · 0.65 mm lead pitch. Use TI drawing 4220204/B for footprint dimensions and tolerances.
Order codes in TI’s 7 October 2026 addendum:
- Active: CD74HC4053PWR, CD74HC4053PWR.A.
- Obsolete: CD74HC4053PW, CD74HC4053PWRG4, CD74HC4053PWT.
- TI CD74HC4053 datasheet (PDF)· SCHS122O, revision O (January 2026), with package option addendum
- TI CD74HC4053 product and ordering information
Pin assignments: Figure and Table 4-3 (p. 5). Switching: Figure 7-3 and Table 7-3 (pp. 24–25). Supply bypass: § 8.3 (p. 27). Order codes and package drawings follow the datasheet.