Spark Logic

74HCT595 connection guide

Wiring for one register or a two-register cascade.

TSSOP-16 (PW)

5.00 × 4.40 mm · 0.65 mm pitch
PW0016A package outline

Connect and bypass the supply

With power off, wire regulated 5 V to 16 VCC and connect 8 GND to the controller ground. Fit one 100 nF ceramic capacitor per IC close to these pins. Use a capacitor rated above the supply (for example, 16 V). Repeat the circuit for each chip.

5 V to pin 16, ground to pin 8 and 100 nF across both pins+5 VGND100 nF16 VCC8 GND

After wiring the logic and before sending clocks, measure VCC relative to pin 8. Expect 4.5–5.5 V. Keep host outputs LOW or high impedance while the register supply is off.

1 QB 2 QC 3 QD 4 QE 5 QF 6 QG 7 QH 8 GND Used in this circuit
16 VCC Used in this circuit15 QA 14 SER 13 /OE 12 RCLK 11 SRCLK 10 /SRCLR 9 QH′
Top view · Pin 1 at upper left · Schematic outline

Wire the data and clocks

Use three push-pull controller signals for data and clocks, with a common ground. A 3.3 V controller can drive the HCT inputs if its guaranteed LOW is ≤ 0.8 V and HIGH is ≥ 2.0 V, and the input transitions meet the 500 ns/V limit. Keep the driven input voltages within the HCT supply rails. The parallel outputs and QH′ are 5 V-domain signals. Use a 5 V-tolerant receiver or level translation.

+5 V connects A 10 /SRCLR. Host data connects A 14 SER. Host shift connects A 11 SRCLK. Host latch connects A 12 RCLK+5 VA·10 /SRCLRHost dataA·14 SERHost shiftA·11 SRCLKHost latchA·12 RCLK

Leave A pin 9 open. The host drives SER, SRCLK and RCLK independently.

Register A

1 QB 2 QC 3 QD 4 QE 5 QF 6 QG 7 QH Used in this circuit8 GND Used in this circuit
16 VCC Used in this circuit15 QA 14 SER Used in this circuit13 /OE Used in this circuit12 RCLK Used in this circuit11 SRCLK Used in this circuit10 /SRCLR Used in this circuit9 QH′
Top view · Pin 1 at upper left · Schematic outline

Keep the outputs off during startup

On each chip, pull 13 /OE up to 5 V with 10 kΩ. Leave the ground jumper open during startup. Tie /SRCLR HIGH. The initial shift and storage words are undefined. With /OE HIGH, QA–QH are high impedance. Add receiver-side bias if a defined load state is required.

If the controller pins float during reset, add a 10 kΩ pulldown to ground on SER, RCLK and each SRCLK line. Check the host’s HIGH level with that load.

10 kΩ pull-up and a normally open jumper from /OE pin 13 to ground. Repeat per chip.+5 V10 kΩPin 13 /OEGNDOpen jumper

Shift, latch and verify

  1. Keep /OE HIGH on each chip. Start with SRCLK and RCLK LOW, and keep RCLK LOW while shifting.
  2. Send 0x80, most significant bit (MSB) first, with 8 rising edges per shift-clock line. At a 1 MHz bench clock, set SER early in the LOW half-cycle and keep it stable until the clock returns LOW.
  3. After the final SRCLK rising edge, wait at least 1 µs in this bench test, then pulse RCLK HIGH for at least 1 µs. Close each /OE jumper to GND only after the latch pulse.
  4. Use a high-impedance probe rated for the 5 V signals and referenced to GND. Expect HIGH at A · 7 QH and LOW on the other parallel outputs. Leave unused outputs open. Send a new word with RCLK LOW to check that the old word stays visible until RCLK rises.

For a shifted pattern, check the bit order and count SRCLK edges. For a stale pattern, check RCLK and /OE. In the cascade, the first byte ends in B and the second in A. See HCT timing limits.

Ordering and documents

TI’s package addendum lists both codes in PW with 2,000 parts per reel.

  • SN74HCT595PWR
  • SN74HCT595PWR.A

Pin map: Figure 5-1 and Table 5-1. Circuit references: §§ 8–11. Ordering: package option addendum. TI documents the separately qualified SN74HCT595-Q1 on its automotive product page.