DRV8825 bipolar stepper motor driver pinout

Two current-regulated bridges drive a bipolar stepper motor. The internal indexer turns STEP and DIR commands into winding currents.

HTSSOP-28 (PWP)

29 contacts Current package

Texas Instruments · 9.7 × 4.4 mm nominal molded body, 0.65 mm lead pitch.

HTSSOP-28 (PWP) pinout

Top view, with pin 1 on the upper left. The exposed thermal pad is underneath the body.
EP is the exposed center pad on the underside.

Selected pin details

2 · CP2

Bidirectional · Bidirectional

Second flying-capacitor terminal. Keep the capacitor close to both leads.

Texas Instruments SLVSA73F, Section 6

Electrical limits · Link to this pin

All 29 pins

Pin	Signal	Direction	Function
1	CP1 Bidirectional	Bidirectional	First flying-capacitor terminal. Fit 10 nF, 50 V between CP1 and CP2.
2	CP2 Bidirectional	Bidirectional	Second flying-capacitor terminal. Keep the capacitor close to both leads.
3	VCP Bidirectional	Bidirectional	Charge pump output for the high-side drive. Connect 100 nF and 1 MΩ in parallel to the motor supply.
4	VMA Supply	Supply	Bridge A motor supply. Tie to VMB and add local bypass.
5	AOUT1 Output	Output	First output of H-bridge A.
6	ISENA Bidirectional	Bidirectional	Bridge A low-side current return and sense. Connect to its own sense resistor to ground.
7	AOUT2 Output	Output	Second output of H-bridge A. The winding connects between AOUT1 and AOUT2.
8	BOUT2 Output	Output	Second output of H-bridge B. The winding connects between BOUT1 and BOUT2.
9	ISENB Bidirectional	Bidirectional	Bridge B low-side current return and sense. Connect to its own sense resistor to ground.
10	BOUT1 Output	Output	First output of H-bridge B.
11	VMB Supply	Supply	Bridge B motor supply. Tie to VMA and add local bypass.
12	AVREF Input	Input	Current reference for winding A.
13	BVREF Input	Input	Current reference for winding B.
14	GND Return	Return	Device ground. Connect both GND pins and the PowerPAD to the board ground.
15	V3P3OUT Output	Output	Internal 3.3 V regulator output. Bypass to ground with 470 nF. Use for low-current reference and pull-up loads.
16	nRESET Input	Input	Active low. Disables both bridges and returns the indexer to its home state.
17	nSLEEP Input	Input	Low enters sleep; high wakes the IC. Allow wake-up before applying STEP.
18	nFAULT Output	Output	Open-drain fault status. Low on overcurrent or thermal shutdown.
19	DECAY Input	Input	Low selects slow decay, open selects mixed decay, high selects fast decay.
20	DIR Input	Input	Determines the indexer direction for the next step.
21	nENBL Input	Input	Low enables motor drive and step indexing. High disables the bridges.
22	STEP Input	Input	A rising edge advances the indexer when the driver is enabled.
23	NC No connection	No connection	No connect.
24	MODE0 Input	Input	Low-order mode selection bit. All three mode pins low select full-step operation.
25	MODE1 Input	Input	Middle mode selection bit.
26	MODE2 Input	Input	High-order mode selection bit.
27	nHOME Output	Output	Open-drain home indicator. Low at the indexer home state.
28	GND Return	Return	Device ground. Connect both GND pins and the PowerPAD to the board ground.
PAD	EP Thermal pad	Thermal pad	Solder the PowerPAD to ground with the thermal layout in Section 11.

Signal assignments

Step and direction

Configure the mode before enabling the bridges. Respect the setup and hold time around STEP.

Winding A

Connect one isolated winding across the two bridge outputs.

Winding B

Connect the other isolated winding across the two bridge outputs.

Status outputs

Read each open-drain signal with its own pull-up.

Electrical limits

Parameter	Limit	Conditions and source
Motor supply8.2–45 V	8.2–45 V	Recommended operating range for VMA and VMB. Texas Instruments SLVSA73F, § 7.3
Digital input low / high≤0.7 V / ≥2.2 V	≤0.7 V / ≥2.2 V	Logic high is specified through 5.25 V. Texas Instruments SLVSA73F, § 7.5
Full-scale winding currentVREF ÷ (5 × RSENSE)	VREF ÷ (5 × RSENSE)	Set separately for the two windings. PCB and thermal conditions limit achievable current. Texas Instruments SLVSA73F, Equation 4
STEP high and low duration1.9 µs minimum each	1.9 µs minimum each	Allow the wake-up interval before sending STEP. Texas Instruments SLVSA73F, § 7.6

Models and documents

This pinout is for the bare PWP IC. A carrier board has its own connector order and sense resistors.

DRV8825PWP: PWP0028C pinout and exposed PowerPAD.
DRV8825PWPR: PWP0028C pinout and exposed PowerPAD.
DRV8825PWPR.A: PWP0028C pinout and exposed PowerPAD.
DRV8825PWPR.B: PWP0028C pinout and exposed PowerPAD.
DRV8825PWPRG4: PWP0028C pinout and exposed PowerPAD.
DRV8825PWPRG4.A: PWP0028C pinout and exposed PowerPAD.
DRV8825PWPRG4.B: PWP0028C pinout and exposed PowerPAD.

Texas Instruments SLVSA73F· Rev. F. Pin functions, timing, mode truth table, current regulation and layout.
Source register· Document revisions, applicable order codes, consulted sections and available file checksums.