ENC28J60 SPI Ethernet controller pinout

The ENC28J60 combines a 10BASE-T MAC and PHY, 8 KiB of packet buffer memory and a host SPI control interface.

SPDIP-28 28 contacts

SOIC-28 28 contacts

SSOP-28 28 contacts

QFN-28

29 contacts Current package

Microchip Technology · Leadless QFN, ML code.

QFN-28 pinout

Locate the pin 1 mark and use the top view unless the drawing specifies a different view.
EP is the exposed center pad on the underside.

Selected pin details

24 · VDD

Supply · Power

3.3 V digital supply.

Microchip DS39662E, Table 1-1

Electrical limits · Link to this pin

All 29 pins

Pin	Signal	Direction	Function
1	NC No connection	No connection	Reserved. Leave disconnected.
2	SO Output	Output	SPI data output. High impedance when CS is high.
3	SI Input	Input	SPI data input.
4	SCK Input	Input	SPI clock input.
5	CS Input	Input	Active-low SPI chip select.
6	RESET Input	Input	Active-low hardware reset with weak internal pull-up.
7	VSSRX Return	Return	Receive PHY ground.
8	TPIN− Input	Input	Negative input of the Ethernet receive pair.
9	TPIN+ Input	Input	Positive input of the Ethernet receive pair.
10	RBIAS Input	Input	Set the PHY bias using a 2.32 kΩ, 1% resistor to ground.
11	VDDTX Supply	Supply	3.3 V transmit PHY supply.
12	TPOUT− Output	Output	Negative output of the Ethernet transmit pair.
13	TPOUT+ Output	Output	Positive output of the Ethernet transmit pair.
14	VSSTX Return	Return	Transmit PHY ground.
15	VDDRX Supply	Supply	3.3 V receive PHY supply.
16	VDDPLL Supply	Supply	3.3 V clock PLL supply.
17	VSSPLL Return	Return	Clock PLL ground.
18	VSSOSC Return	Return	Oscillator ground.
19	OSC1 Input	Input	Input of the 25 MHz crystal oscillator or external clock.
20	OSC2 Output	Output	Oscillator output. Leave open when OSC1 uses an external clock.
21	VDDOSC Supply	Supply	3.3 V oscillator supply.
22	LEDB Output	Output	Programmable PHY status LED output. Its external load can affect reset strapping.
23	LEDA Output	Output	Programmable PHY status LED output.
24	VDD Supply	Supply	3.3 V digital supply.
25	VCAP Regulator output	Regulator output	Internal 2.5 V regulator output. Fit a low-ESR 10 µF capacitor to ground. Do not power an external load from this pin.
26	VSS Return	Return	Digital ground.
27	CLKOUT Output	Output	Programmable divided clock output.
28	INT Output	Output	Active-low interrupt output.
PAD	EP Thermal pad	Thermal pad	Exposed back pad. Solder it to VSS.

Signal assignments

Host SPI

Use CS to frame the instruction, address and data bytes.

10BASE-T PHY

Follow the external circuit in Figure 2-4 for 1:1 center-tapped Ethernet magnetics and the terminations.

Electrical limits

Parameter	Limit	Conditions and source
Supply3.10–3.60 V	3.10–3.60 V	All supply domains use the nominal 3.3 V rail. Microchip DS39662E, Table 16-2
Oscillator input25 MHz	25 MHz	Use a parallel-resonant crystal or a compliant external CMOS clock. Microchip DS39662E, § 2.1
SPI clock20 MHz maximum	20 MHz maximum	Review the silicon-revision errata before lowering the host clock on older silicon. Microchip DS39662E, SPI timing and DS80349

Models and documents

The through-hole, gull-wing and QFN packages have separate mechanical drawings. The QFN pin numbers are shifted and its exposed pad connects to VSS.

ENC28J60-I/ML: Industrial QFN.
ENC28J60T-I/ML: Industrial QFN.

Microchip DS39662E· Table 1-1 pin assignments; § 2 external components; SPI; package and order information.
Microchip ENC28J60 document list· Includes DS80349 silicon errata and packaging resources.
Source register· Document revisions, applicable order codes, consulted sections and available file checksums.