Spark Logic

MX25U4033EZBI-12G pinout

Macronix 1.8 V, 4 Mbit serial NOR flash with single SPI, dual I/O and quad I/O.

SOP-8 8 contacts
USON-8 (4 × 4) 9 contacts

USON-8 (4 × 3)

9 contacts Current package
WSON-8 (6 × 5) 9 contacts
WLCSP-8 8 contacts

Macronix · 0.80 mm land pitch · Macronix outline p. 66

USON-8 (4 × 3) pinout

Leave the exposed metal floating or connect it to the same ground as pin 4. Avoid routing traces or placing vias directly under the pad. Pin 4 remains the required GND terminal.

USON-8 (4 × 3) · Top view (marking side) · index at pin 1.
Dashed outline shows the underside pad schematically. See the package drawing for the footprint.
Selected pin details

2 · SO/SIO1

Output / bidirectional · Bidirectional

MISO in single SPI. SIO1 takes address bits in dual and quad I/O reads and drives returned data. High impedance when deselected.

Macronix PM1755 rev. 1.9 · §§3–4, 8–10

Electrical limits · Link to this pin

Open this wiring example

Power, ground and chip select

  • 1.8 V
    • Regulator output
    • C1.1
    • R1.1
  • Ground
    • Supply return
    • Host ground
    • C1.2
  • CS# idle bias
    • →
    • R1.2
C1 · 100 nF between 1.8 V and Ground1.8 VC1 · 100 nFGround
R1 · 10 kΩ between 1.8 V and CS# idle bias1.8 VR1 · 10 kΩCS# idle bias

Connection guide

All 9 pins

PinSignalDirectionFunction
1CS# InputInput Active low. Keep high when idle and during power transitions; a low pulse frames one transaction.
2SO/SIO1 Output / bidirectionalOutput / bidirectional MISO in single SPI. SIO1 takes address bits in dual and quad I/O reads and drives returned data. High impedance when deselected.
3WP#/SIO2 Input / bidirectionalInput / bidirectional With QE = 0, a low level can lock status-register writes when SRWD = 1 in BP protection mode; it does not by itself protect the whole array. With QE = 1, use as SIO2. Internally pulled high in its control role.
4GND ReferenceReference Required supply return and logic reference. Connect to host and supply ground.
5SI/SIO0 Input / bidirectionalInput / bidirectional MOSI in single SPI. SIO0 also drives data back to the host during dual and quad I/O reads.
6SCLK InputInput Host clock. The flash samples input on rising edges and changes output on falling edges. Use SPI mode 0 or 3.
7HOLD#/SIO3 Input / bidirectionalInput / bidirectional With QE = 0, an active-low pause while CS# is low. Change HOLD# with SCLK low for immediate entry or exit. With QE = 1, use as SIO3. Internally pulled high in its control role.
8VCC SupplySupply Regulated 1.65–2.00 V. Bypass locally to the numbered or ball GND terminal. Never connect to a 3.3 V supply.
EPExposed pad Underside metalUnderside metal Leave the exposed metal floating or connect it to the same ground as pin 4. Avoid routing traces or placing vias directly under the pad. Pin 4 remains the required GND terminal.

Signal assignments

Dual I/O read

Use the same pins as single SPI, but route SIO0 and SIO1 to bidirectional host lines. The flash receives the opcode on SIO0, then receives the address and returns data over both lines.

Electrical limits

ParameterLimitConditions and source
Operating supply1.65–2.00 V1.65–2.00 V Nominal 1.8 V; industrial range −40 to +85 °C. Macronix PM1755 rev. 1.9 · §1 and Table 13
Input thresholdsLOW ≤ 0.3 × VCC; HIGH ≥ 0.7 × VCCLOW ≤ 0.3 × VCC; HIGH ≥ 0.7 × VCC At 1.8 V: LOW ≤ 0.54 V; HIGH ≥ 1.26 V. Use host outputs within the flash supply rails. Macronix PM1755 rev. 1.9 · Table 13
Output levelsLOW ≤ 0.2 V; HIGH ≥ VCC − 0.2 VLOW ≤ 0.2 V; HIGH ≥ VCC − 0.2 V DC test loads: IOL = 100 µA and IOH = −100 µA. Check host thresholds in the reverse direction. Macronix PM1755 rev. 1.9 · Table 13
Startup delay≥ 300 µs≥ 300 µs From VCC reaching 1.65 V to the first CS# assertion (characterized). Macronix PM1755 rev. 1.9 · Table 15
SCLK limits50 MHz / 80 MHz / 70 MHz50 MHz / 80 MHz / 70 MHz 50 MHz for 03h READ, 80 MHz for 0Bh FAST_READ and BBh 2READ, 70 MHz for EBh 4READ and 38h 4PP. Apply the relevant AC timing and load conditions. Macronix PM1755 rev. 1.9 · Table 14
Array organization4 Mbit (512 KiB)4 Mbit (512 KiB) 256-byte program pages; 4 KiB sectors, 32 KiB and 64 KiB erase blocks. Main array offsets 000000h–07FFFFh. Macronix PM1755 rev. 1.9 · Table 4
Program and erase time3 ms page program; 200 ms sector erase3 ms page program; 200 ms sector erase Maximum page program and 4 KiB erase times at 85 °C and 1.65 V. Poll WIP and verify before using programmed data. Macronix PM1755 rev. 1.9 · §15
Power-up stateStandby, WEL clearedStandby, WEL cleared QE and protection configuration are nonvolatile. Factory status is 00h and the array is erased; verify used parts before assuming defaults. There is no reset pin or software reset command. Macronix PM1755 rev. 1.9 · §§6, 10, 13 and Table 12

Models and documents

PM1755 rev. 1.9 lists five orderable package codes: M1, ZU, ZB, ZN and BA. Select the actual package before wiring; USON and WSON exposed-metal rules differ.

MX25U4033EZBI-12G
USON-8 (4 × 3) · −40 to +85 °C · speed code 12 (command-dependent limits) · RoHS compliant and halogen-free.