USB full-speed
Micro-USB uses the MCU full-speed PHY on PA11 (D−) and PA12 (D+). The rear pads duplicate the connector signals. The STM32 high-speed controller requires a separate PHY for high-speed USB.
1Bitsy pinout
The 1Bitsy v1.0d exposes STM32F415 GPIO, analog inputs, serial buses, USB and Cortex debug on a breadboard-friendly module.
1Bitsy v1.0d
74 contacts Current package1Bitsy v1.0d pinout
Lower expansion holes · inner row
Lower expansion holes · outer row
X3 Cortex debug header · upper row
X3 Cortex debug header · lower row
P24 Micro-USB B
Auxiliary GPIO and switch
Rear USB pads
Rear debug pads
Rear boot jumper and RTC footprint
38 · PA7
ADC channel 7, SPI1 MOSI (AF5), or TIM3 channel 2 (AF2).
All 74 pins
| Pin | Signal | Direction | Function |
|---|---|---|---|
| 1 | GND Supply return | Supply return | Common return for the regulator, MCU, and external signal equipment. |
| 2 | PC10 Bidirectional | Bidirectional | USART3 TX (AF7), UART4 TX (AF8), SPI3 SCK (AF6), or SDIO D2 (AF12). |
| 3 | PC11 Bidirectional | Bidirectional | USART3 RX (AF7), UART4 RX (AF8), SPI3 MISO (AF6), or SDIO D3 (AF12). |
| 4 | PC12 Bidirectional | Bidirectional | USART3 CK (AF7), UART5 TX (AF8), SPI3 MOSI (AF6), or SDIO CK (AF12). |
| 5 | PD2 Bidirectional | Bidirectional | SDIO CMD (AF12), UART5 RX (AF8), or TIM3 external trigger (AF2). |
| 6 | PB4 Bidirectional | Bidirectional | SPI1 MISO (AF5), SPI3 MISO (AF6), or JTAG reset NJTRST (AF0). Reconfigure after reset when using it for SPI. |
| 7 | PB5 Bidirectional | Bidirectional | SPI1 MOSI (AF5), SPI3 MOSI (AF6), or CAN2 RX (AF9). |
| 8 | PB6 Bidirectional | Bidirectional | I²C1 SCL (AF4), USART1 TX (AF7), or CAN2 TX (AF9). |
| 9 | PB7 Bidirectional | Bidirectional | I²C1 SDA (AF4) or USART1 RX (AF7). |
| 10 | PB8 Bidirectional | Bidirectional | I²C1 SCL (AF4), CAN1 RX (AF9), or SDIO D4 (AF12). |
| 11 | PB9 Bidirectional | Bidirectional | I²C1 SDA (AF4), CAN1 TX (AF9), SPI2 NSS (AF5), or SDIO D5 (AF12). |
| 12 | PC2 Bidirectional | Bidirectional | ADC channel 12, SPI2 MISO (AF5), or I²S2 extended SD (AF6). |
| 13 | PC3 Bidirectional | Bidirectional | ADC channel 13 or SPI2 MOSI / I²S2 SD (AF5). |
| 14 | VBAT Backup supply | Backup supply | Optional RTC and backup-domain supply. It does not power the MCU core or the board’s 3.3 V rail. |
| 15 | 3V3 Regulated rail | Regulated rail | Shared 3.3 V regulator output at contacts 15 and 29. Verify regulator headroom and the total load before powering peripherals. |
| 16 | GND Supply return | Supply return | Common return for the regulator, MCU, and external signal equipment. |
| 17 | PB0 Bidirectional | Bidirectional | ADC channel 8, TIM1 complementary channel 2 (AF1), or TIM3 channel 3 (AF2). |
| 18 | PB1 Bidirectional | Bidirectional | ADC channel 9, TIM1 complementary channel 3 (AF1), or TIM3 channel 4 (AF2). |
| 19 | PB10 Bidirectional | Bidirectional | I²C2 SCL (AF4), SPI2 SCK / I²S2 CK (AF5), or USART3 TX (AF7). |
| 20 | PB11 Bidirectional | Bidirectional | I²C2 SDA (AF4), USART3 RX (AF7), or TIM2 channel 4 (AF1). |
| 21 | PB12 Bidirectional | Bidirectional | SPI2 NSS / I²S2 WS (AF5), CAN2 RX (AF9), or TIM1 break input (AF1). |
| 22 | PB13 Bidirectional | Bidirectional | SPI2 SCK / I²S2 CK (AF5), USART3 CTS (AF7), or CAN2 TX (AF9). |
| 23 | PB14 Bidirectional | Bidirectional | SPI2 MISO (AF5), I²S2 extended SD (AF6), or TIM12 channel 1 (AF9). |
| 24 | PB15 Bidirectional | Bidirectional | SPI2 MOSI / I²S2 SD (AF5) or TIM12 channel 2 (AF9). |
| 25 | PC6 Bidirectional | Bidirectional | USART6 TX (AF8), SDIO D6 (AF12), or TIM3 channel 1 (AF2). |
| 26 | PC7 Bidirectional | Bidirectional | USART6 RX (AF8), SDIO D7 (AF12), or TIM3 channel 2 (AF2). |
| 27 | PC8 Bidirectional | Bidirectional | USART6 CK (AF8), SDIO D0 (AF12), or TIM3 channel 3 (AF2). |
| 28 | PC9 Bidirectional | Bidirectional | I²C3 SDA (AF4), SDIO D1 (AF12), or MCU clock output MCO2 (AF0). |
| 29 | 3V3 Regulated rail | Regulated rail | Shared 3.3 V regulator output at contacts 15 and 29. Verify regulator headroom and the total load before powering peripherals. |
| 30 | VIN Supply input | Supply input | Board regulator input downstream of the USB isolation diode. Use the Micro-USB connector for the documented power-up procedure. |
| 31 | PA0 Bidirectional | Bidirectional | ADC channel 0, UART4 TX (AF8), TIM5 channel 1 (AF2), or Standby wakeup input. |
| 32 | PA1 Bidirectional | Bidirectional | ADC channel 1, UART4 RX (AF8), or TIM5 channel 2 (AF2). |
| 33 | PA2 Bidirectional | Bidirectional | ADC channel 2, USART2 TX (AF7), or TIM5 channel 3 (AF2). |
| 34 | PA3 Bidirectional | Bidirectional | ADC channel 3, USART2 RX (AF7), or TIM5 channel 4 (AF2). |
| 35 | PA4 Bidirectional | Bidirectional | ADC channel 4, DAC channel 1, SPI1 NSS (AF5), or SPI3 NSS (AF6). |
| 36 | PA5 Bidirectional | Bidirectional | ADC channel 5, DAC channel 2, or SPI1 SCK (AF5). |
| 37 | PA6 Bidirectional | Bidirectional | ADC channel 6, SPI1 MISO (AF5), or TIM3 channel 1 (AF2). |
| 38 | PA7 Bidirectional | Bidirectional | ADC channel 7, SPI1 MOSI (AF5), or TIM3 channel 2 (AF2). |
| 39 | PC4 Bidirectional | Bidirectional | ADC channel 14 or GPIO. |
| 40 | PC5 Bidirectional | Bidirectional | ADC channel 15 or GPIO. |
| X3-1 | VTref Reference output | Reference output | Board 3.3 V target-reference output for the probe. |
| X3-2 | SWDIO Bidirectional | Bidirectional | Serial Wire Debug data, wired to PA13. JTAG uses it as JTMS. |
| X3-3 | DBG_GND Supply return | Supply return | Debug probe ground. |
| X3-4 | SWCLK Input | Input | Serial Wire Debug clock, wired to PA14. JTAG uses it as JTCK. |
| X3-5 | DBG_GND Supply return | Supply return | Debug probe ground. |
| X3-6 | SWO Output | Output | Optional serial wire trace output on PB3. JTAG uses it as JTDO. |
| X3-7 | KEY Key position | Key position | Position 7 is the mechanical key. The corresponding PCB footprint land is on ground. |
| X3-8 | JTDI Input | Input | JTAG data input on PA15. Leave unused for Serial Wire Debug. |
| X3-9 | GNDDetect Reference | Reference | Probe ground-detect position, tied to board ground. |
| X3-10 | NRST Reset input | Reset input | Active-low system reset. Use an open-drain reset driver or the probe’s specified reset output. |
| P24-1 | USB_VBUS Supply input | Supply input | 5 V from the USB host. The on-board diode feeds the VIN rail from VBUS. |
| P24-2 | USB_DM Bidirectional | Bidirectional | USB full-speed D−, wired to PA11. Route as a pair with D+ when using the rear pads. |
| P24-3 | USB_DP Bidirectional | Bidirectional | USB full-speed D+, wired to PA12. Route as a pair with D− when using the rear pads. |
| P24-4 | USB_ID Input | Input | USB ID, wired to PA10. Use a Micro-B data cable for USB device mode. |
| P24-5 | USB_GND Supply return | Supply return | USB connector return, bonded to board ground. |
| P9 | PA8 Bidirectional | Bidirectional | I²C3 SCL (AF4), MCO1 (AF0), or onboard status LED control. The LED lights when PA8 sinks current through R4. |
| P10 | PC0 Bidirectional | Bidirectional | ADC channel 10 or GPIO. Top-side through-hole near PC2 and PC3. |
| P23 | PC13 Bidirectional | Bidirectional | RTC tamper or GPIO. Follow the MCU datasheet’s PC13–PC15 current, load and speed restrictions. |
| P27 | PB2 Bidirectional | Bidirectional | GPIO and BOOT1 strap. The board has a 10 kΩ pull-down. Keep it low while selecting the ROM bootloader. |
| SW1-2 | PC1 Input | Input | User pushbutton node. The 10 kΩ pull-up reads HIGH when released and LOW when pressed. PC1 also supports ADC channel 11. |
| P43 | SWDIO Bidirectional | Bidirectional | Serial Wire Debug data, wired to PA13. JTAG uses it as JTMS. |
| P44 | SWCLK Input | Input | Serial Wire Debug clock, wired to PA14. JTAG uses it as JTCK. |
| P45 | SWO Output | Output | Optional serial wire trace output on PB3. JTAG uses it as JTDO. |
| P46 | JTDI Input | Input | JTAG data input on PA15. Leave unused for Serial Wire Debug. |
| P47 | NRST Reset input | Reset input | Active-low system reset. Use an open-drain reset driver or the probe’s specified reset output. |
| P48 | USB_VBUS Supply input | Supply input | 5 V from the USB host. The on-board diode feeds the VIN rail from VBUS. |
| P49 | USB_DM Bidirectional | Bidirectional | USB full-speed D−, wired to PA11. Route as a pair with D+ when using the rear pads. |
| P50 | USB_DP Bidirectional | Bidirectional | USB full-speed D+, wired to PA12. Route as a pair with D− when using the rear pads. |
| P51 | USB_ID Input | Input | USB ID, wired to PA10. Use a Micro-B data cable for USB device mode. |
| P52 | USB_GND Supply return | Supply return | USB connector return, bonded to board ground. |
| J1-1 | DFU_VBUS Jumper supply | Jumper supply | USB VBUS side of the BOOT0 jumper. |
| J1-2 | DFU_COUPLE Jumper node | Jumper node | Couples the USB power-up edge through C15 to BOOT0. Close J1 before connecting USB to request the ROM bootloader. |
| X1-1 | PC15 Oscillator output | Oscillator output | Optional 32.768 kHz low-speed external oscillator output, with the associated load capacitor footprint. |
| X1-2 | PC14 Oscillator input | Oscillator input | Optional 32.768 kHz low-speed external oscillator input, with the associated load capacitor footprint. |
Signal assignments
SWD / JTAG
Use SWDIO and SWCLK with ground and VTref. NRST supports connect-under-reset and SWO is optional. JTAG also uses JTDI and JTDO. PB4 is NJTRST when configured for JTAG.
UART / USART
Use PB6/PB7 for USART1, PA2/PA3 for USART2, and PC10/PC11 or PB10/PB11 for USART3. These TX/RX pairs use AF7.
For AF8, use PA0/PA1 or PC10/PC11 for UART4, PC12/PD2 for UART5, and PC6/PC7 for USART6.
Cross TX to RX and share ground with a 3.3 V logic-level endpoint.
I²C
Use AF4, open-drain signaling and external pull-ups. Select PB6/PB7 or PB8/PB9 for I²C1, or PB10/PB11 for I²C2. I²C3 is available on PA8/PC9, but the onboard status LED loads PA8.
SPI
For SPI1 use PA5/PA6/PA7 (SCK/MISO/MOSI) in AF5. For SPI2 use PB13/PB14/PB15 in AF5. For SPI3 use PC10/PC11/PC12 in AF6. Select a compatible NSS pin or drive chip select from an independent GPIO.
CAN
CAN1 RX/TX uses PB8/PB9 in AF9. CAN2 RX/TX uses PB5/PB6 or PB12/PB13 in AF9. Connect to an external CAN transceiver and use termination appropriate to the bus.
SDIO
For an SD card, use PC8–PC11 as D0–D3, PC12 as CK and PD2 as CMD, all in AF12. PB8/PB9 and PC6/PC7 provide D4–D7 for wider interfaces that support them.
ADC and DAC
ADC channels 0–7 are on PA0–PA7, 8–9 on PB0/PB1, and 10–15 on PC0–PC5. The on-board button and pull-up share PC1. DAC1 and DAC2 are on PA4 and PA5. Configure analog mode and stay within the analog supply rails.
RTC and backup
VBAT can preserve the RTC and configured backup SRAM when main power is absent. PC14 and PC15 are on the optional low-speed crystal footprint. Use the 32.768 kHz nominal frequency shown on the schematic and silkscreen.
Electrical limits
| Parameter | Limit | Conditions and source |
|---|---|---|
| Board logic rail3.3 V nominal | 3.3 V nominal | Regulator output. The schematic uses an unqualified regulator symbol, so check the fitted regulator and board power budget before loading 3V3 or choosing an alternate VIN source. 1Bitsy v1.0d schematic |
| GPIO levels for examples0–3.3 V | 0–3.3 V | Share ground and use logic-level signals. ST qualifies input tolerance per MCU pad, supply state and mode. Use a level translator when the peripheral requires another voltage. ST DS8597 Rev 9, Tables 7, 11 and 48 |
| ADC input rangeVSSA to VREF+ | VSSA to VREF+ | The board derives its analog supply from the 3.3 V rail through a ferrite. Set the ADC sample time for the source impedance and resolution. ST DS8597 Rev 9, Table 67; 1Bitsy v1.0d schematic |
| VBAT operating range1.65–3.6 V | 1.65–3.6 V | At the MCU backup input. With no separate backup supply, ST recommends tying VBAT to VDD. ST DS8597 Rev 9, Table 14 and Fig. 21 |
| Main and optional RTC crystals25 MHz HSE · 32.768 kHz LSE | 25 MHz HSE · 32.768 kHz LSE | The HSE is fitted by design. The LSE footprint and its load-capacitor positions are optional. Choose capacitors for the fitted crystal and stray capacitance. 1Bitsy v1.0d schematic |
| Reset and default debugNRST active LOW | NRST active LOW | Leave the BOOT0 jumper open for normal boot from Flash with the board’s default straps. The STM32 assigns its reset debug pins to the SWJ debug function. 1Bitsy v1.0d schematic; ST DS8597 Rev 9, Tables 7 and 9 |
Models and documents
Board revision v1.0d with STM32F415RGT6. Numbered contacts use the official board legend. IDs beginning with P, X, J or SW refer to PCB designators. The hardware archive also documents revisions v1.0a, v1.0b and v1.0c. Confirm the revision on the back before using this map.
- 1Bitsy v1.0d
- STM32F415RGT6 · 1 MiB Flash · 192 KiB SRAM including 64 KiB CCM · 4 KiB backup SRAM.
- 1Bitsy v1.0d pinout legend· 2016 · Numbered headers, front and back pads · Piotr Esden-Tempski and 1BitSquared, CC BY-SA 4.0.
- 1Bitsy v1.0d schematic· Rev. v1.0d · USB power path, boot jumper, X3, LED, button and clock circuits · Piotr Esden-Tempski and 1BitSquared, CC BY-SA 4.0.
- 1Bitsy hardware archive· KiCad layout and schematics for PCB revisions v1.0a through v1.0d.
- 1Bitsy Quickstart Guide· Black Magic Probe and factory-firmware DFU procedure.
- STM32F415RG datasheet· ST DS8597 Rev 9 · LQFP64 pin functions, alternate function tables and electrical limits.
- STM32F415 reference manual and errata· RM0090 and ES0182 · Configuration and silicon-revision-specific restrictions.
- I²C bus specification and user manual· NXP UM10204 Rev 7 · Standard-mode bus timing and pull-up sizing.
- 1Bitsy source register· Revisions, original URLs, licensing and file checksums.