74HC595 connection guide
Wire a TI SN74HC595 in PDIP-16 for shifting, cascading, output enable and reset.
Connect and bypass the supply
With power off, connect a regulated 4.5 V supply to 16 VCC and its return to 8 GND. Fit one 100 nF ceramic capacitor (X7R, ≥10 V) across these pins on each chip. Connect controller and instrument grounds to the same return.
Complete the selected wiring below before applying power. With power on, verify 4.5 V at pin 16 with meter common at pin 8.
Initialize with outputs disabled
Use fast, rail-compatible controller outputs and ensure DATA, SHIFT, LATCH and CLEAR have defined states during startup. Keep SHIFT and LATCH LOW until power is stable. Provide defined HIGH or LOW levels with controller-side pulls if its pins float at boot. Each 10 kΩ ±1% ENABLE pull-up holds /OE HIGH while the controller pin is high impedance. It draws up to 0.46 mA at 4.5 V when driven LOW (0.91 mA for two pull-ups). Choose a GPIO that can sink this current and still meet VIL.
The stored byte at power-up is unspecified. With /OE HIGH and /SRCLR HIGH, shift eight zeros per chip and pulse LATCH once before driving /OE LOW. Add a defined inactive bias at any load that needs a known state during high impedance. Apply controller signals only while the register is powered.
Choose a wiring scenario
Matching VCC, SHIFT, LATCH, ENABLE and CHAIN labels are common nets across the drawings. Supply and ground follow the circuit above for each chip. Unused outputs can be left open.
U1 wiring
| Pin | Net | Connect to |
|---|---|---|
| 14 SER | DATA | Controller data output |
| 11 SRCLK | SHIFT | Controller shift clock |
| 12 RCLK | LATCH | Controller storage clock |
| 10 /SRCLR | VCC | Tie HIGH to VCC |
| 13 /OE | ENABLE | Controller output enable, with 10 kΩ to VCC |
| 9 QH′ | CHAIN | U2 pin 14 (SER) |
14 SER11 SRCLK12 RCLK10 /SRCLR13 /OE9 QH′15 QA1 QB2 QC3 QD4 QE5 QF6 QG7 QH
Arrows show signal direction between paired pins.
SER → QH′ shows the clocked data path inside U1. CHAIN connects U1 QH′ to U2 SER.
U2 wiring
| Pin | Net | Connect to |
|---|---|---|
| 14 SER | CHAIN | U1 pin 9 (QH′) |
| 11 SRCLK | SHIFT | Controller shift clock |
| 12 RCLK | LATCH | Controller storage clock |
| 10 /SRCLR | VCC | Tie HIGH to VCC |
| 13 /OE | ENABLE | Controller output enable, with 10 kΩ to VCC |
| 15 QA | PROBE | QA shown. Probe QA–QH one at a time, referenced to GND. |
14 SER11 SRCLK12 RCLK10 /SRCLR13 /OE15 QA1 QB2 QC3 QD4 QE5 QF6 QG7 QH
Run the test
Start at 100 kHz and allow at least 1 µs between the last shift edge and the latch edge.
- Wire U1 pin 9 to U2 pin 14. Fan out SHIFT, LATCH and ENABLE from the same controller to both chips. Each chip needs its own bypass capacitor and ENABLE pull-up.
- Send the far byte 0x96 first and the near byte 0x21 second, each most significant bit first. Keep LATCH LOW for all 16 shift edges, then pulse it HIGH once.
- Use short wires. At 4.5 V and 50 pF, budget 40 ns maximum SRCLK-to-QH′ delay plus 25 ns SER setup, then add wiring delay, clock skew and margin. Check hold time as well when distributing the clock.
After LATCH, U2 has QB, QC, QE and QH HIGH. U1 has QA and QF HIGH. Use a high-impedance probe relative to pin 8 of either chip. Leave U2 pin 9 open.
For checks at 4.5 V with a probe load ≤20 µA, driven LOW is ≤0.1 V and driven HIGH is ≥4.4 V. Use a logic analyzer or oscilloscope for edges and a meter for settled states. If the pattern is wrong, check VCC, /OE and /SRCLR before counting SHIFT edges and checking LATCH.
Package and documents
TI package code N · 19.31 × 6.35 mm nominal body · 2.54 mm lead pitch. See the TI package drawing for footprint dimensions and tolerances.
Catalog SN74HC595 ordering suffixes for this package in the TI 18 September 2026 addendum. Active: N, N.A, NE4.
- TI SNx4HC595 datasheet (PDF)· SCLS041J, October 2021, with package option addendum
- TI SN74HC595 product and ordering information
Related TI lines have separate documentation, including the SN74HC595B in X1QFN and SN74HC595-EP. The SN54HC595 military pinouts are in §5 of SCLS041J.