Spark Logic

74HC595 connection guide

Wire a TI SN74HC595 in PDIP-16 for shifting, cascading, output enable and reset.

Connect and bypass the supply

With power off, connect a regulated 4.5 V supply to 16 VCC and its return to 8 GND. Fit one 100 nF ceramic capacitor (X7R, ≥10 V) across these pins on each chip. Connect controller and instrument grounds to the same return.

4.5 V at pin 16 and ground at pin 8, with 100 nF across the pins4.5 VCommon GND100 nF16 VCC8 GND

Complete the selected wiring below before applying power. With power on, verify 4.5 V at pin 16 with meter common at pin 8.

1 QB 2 QC 3 QD 4 QE 5 QF 6 QG 7 QH 8 GND Used in this circuit
16 VCC Used in this circuit15 QA 14 SER 13 /OE 12 RCLK 11 SRCLK 10 /SRCLR 9 QH′
Top view · Pin 1 at upper left · Schematic outline

Initialize with outputs disabled

Use fast, rail-compatible controller outputs and ensure DATA, SHIFT, LATCH and CLEAR have defined states during startup. Keep SHIFT and LATCH LOW until power is stable. Provide defined HIGH or LOW levels with controller-side pulls if its pins float at boot. Each 10 kΩ ±1% ENABLE pull-up holds /OE HIGH while the controller pin is high impedance. It draws up to 0.46 mA at 4.5 V when driven LOW (0.91 mA for two pull-ups). Choose a GPIO that can sink this current and still meet VIL.

The stored byte at power-up is unspecified. With /OE HIGH and /SRCLR HIGH, shift eight zeros per chip and pulse LATCH once before driving /OE LOW. Add a defined inactive bias at any load that needs a known state during high impedance. Apply controller signals only while the register is powered.

Choose a wiring scenario

Matching VCC, SHIFT, LATCH, ENABLE and CHAIN labels are common nets across the drawings. Supply and ground follow the circuit above for each chip. Unused outputs can be left open.

U1 wiring

U1 signal wiring, listed in the table belowU1DATA14 SERSHIFT11 SRCLKLATCH12 RCLKVCC10 /SRCLRENABLE13 /OE10 kΩVCC15 QAPROBE10 kΩ
PinNetConnect to
14 SERDATA Controller data output
11 SRCLKSHIFT Controller shift clock
12 RCLKLATCH Controller storage clock
10 /SRCLRVCC Tie HIGH to VCC
13 /OEENABLE Controller output enable, with 10 kΩ to VCC
15 QAPROBE Probe QA with 10 kΩ to GND

14 SER11 SRCLK12 RCLK10 /SRCLR13 /OE15 QA

1 QB 2 QC 3 QD 4 QE 5 QF 6 QG 7 QH 8 GND
16 VCC 15 QA Used in this circuit14 SER Used in this circuit13 /OE Used in this circuit12 RCLK Used in this circuit11 SRCLK Used in this circuit10 /SRCLR Used in this circuit9 QH′
Top view · Pin 1 at upper left · Schematic outline

Run the test

Start at 100 kHz and allow at least 1 µs between the last shift edge and the latch edge.

  1. Add a 10 kΩ ±1% pull-down from QA to GND. Shift and latch 0x01 with ENABLE HIGH, then drive ENABLE LOW. QA now sources current through the pull-down.
  2. Drive ENABLE HIGH and back LOW without pulsing either clock. This changes the parallel output drivers while preserving the stored byte and the active QH′ driver.

QA reads HIGH when enabled (at least 3.84 V at 4.5 V with the indicated light resistive load). With ENABLE HIGH, the resistor pulls the undriven node toward ground. QA returns HIGH when enabled again. At 4.5 V, the pull-down draws at most 0.46 mA and dissipates under 2.1 mW; a ⅛ W resistor is sufficient.

For checks at 4.5 V with a probe load ≤20 µA, driven LOW is ≤0.1 V and driven HIGH is ≥4.4 V. Use a logic analyzer or oscilloscope for edges and a meter for settled states. If the pattern is wrong, check VCC, /OE and /SRCLR before counting SHIFT edges and checking LATCH.

Clock and clear timing · Output load limits

Package and documents

TI package code N · 19.31 × 6.35 mm nominal body · 2.54 mm lead pitch. See the TI package drawing for footprint dimensions and tolerances.

Catalog SN74HC595 ordering suffixes for this package in the TI 18 September 2026 addendum. Active: N, N.A, NE4.

Related TI lines have separate documentation, including the SN74HC595B in X1QFN and SN74HC595-EP. The SN54HC595 military pinouts are in §5 of SCLS041J.